2
Specifications
2.1 Inputs
Input
proceeds -5mV to about -3.0V linear pulses (ref. to the common
mode range of ultra fast comparators),
rise time ≥ 700ps typically,
Z
in
= 50Ω; dc-coupled front panel BNC connector;
minimum input width ≥ 1 ns,
in the LET mode the CFD 2128N accepts shorter input pulses
Delay
two BNC connectors for an external delay cable in order to form the
internal constant fraction signal. For specific length see section
4.2.3.
2.2 Outputs
Inspect
displays output signal of zero crossing discriminator for use in
trimming the time walk.
Neg. outputs
t
wo independent negative current outputs, each providing -32mA
into 50Ω, rise time ≈ 2 ns, pulse width ≤ 5 ns nominal (for longer
pulse width capacitor C
4
has to be changed).
Pos. outputs
two independent positive voltage outputs, providing 2V into 50Ω,
rise time ≈ 4 ns, width adjustable by front panel trimming
potentiometer, the width then determines the internal dead time.
The maximum width should not exceed 300 ns.
2.3 Controls
Threshold
front panel 10-turn locking dial potentiometer to set acceptance
level for input pulses (range ≈ -5 mV to -1V)
Walk adjust
f
ront panel trimming potentiometer (screwdriver) to compensate
walk of the internal zero crossing discriminator
CFT-CFRR-LET
front panel three position switch to select basic constant fraction
timing (CFT), constant fraction with slow rise time reject (CFRR) or
leading edge timing (LET)
Width
front panel trimming potentiometer (screwdriver) to set the width of
the positive output pulse. The width determines the internal dead
time.
2.4 Indicators
Rate
LED indicates activity of the discriminator, colour of LED changes by
count rate; yellow-green up to ≈ 5 kHz, orange 5 to about 10 kHz,
red above 10 kHz
F
ComTec GmbH
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