Circuit description
5
Circuit description
5.1 General
The model 2128N provides the advantage that various modes of operation (CFT, CFRR, LET) can
be chosen by selecting the front panel switch. The fraction (factory set to f = 0.4) can be changed
with the resistors R
1
and R
2
on the printed board. This model utilizes a direct coupled negative input
to perform integral discrimination or/and to derive a constant fraction timing mark. The bulk of the
logic signal processing is executed in emitter-coupled fast integrated circuit logic (ECL using SMD
parts). Reference diodes are used to pin all threshold voltages.
5.2 LET mode
Since the model can be operated in various modes, its operation is best appreciated by
understanding the simple LET mode. The input signal is split in a network to serve the two identical
ultra fast comparators (IC1 and IC2, see figure). In the LET mode, both pulse amplitude
discrimination and timing are derived in the comparator IC1. The pulse acceptance level is
established by the front panel threshold potentiometer from -5 mV to – 1.0 V dc. Since the timing
mark for the comparator is derived from the point where the pulse intercepts the threshold setting, it
is quite obvious that the timing mark changes with amplitude and rise time of the input pulse. The
output signal of the comparator (IC1) is accepted through gate IC3 (1/4 of a 10H102) appearing at
the outputs as positive going signal (- 1.7 V to – 0.8 V) and as negative going signal (- 0.8V to -
1.7V). The width of these signals depends on the setting of the leading edge width potentiometer on
the printed board (factory set to about 20ns).
The width can be monitored with a signal probe on the scope. It is recommended, to set the width as
wide as the input signal. The negative output signal of IC3 is accepted through the gate IC6. Note
that with the LET mode (front panel switch) the outputs of the gates IC4 and IC5 are always set to
logic LOW (- 1.7V). The output of gate IC6 is fed to the clock input of a master-slave type D flip-flop
IC7 (1/2 of 10H131). The Q – output is fed to a bus driver (10192) and converting the ECL levels to
fast NIM levels (- 32 mA in 50Ω). The width of the output pulse is either determined by a RC
combination. The output of IC7 goes to the clock enable input of a second master-slave flip-flop IC8
(second half of the 10H131). The output of IC8 is converted by the following ECL - to – TTL
translator (10H125) to positive TTL output pulses. The width of the positive output signal is set by the
front panel potentiometer (WIDTH control). This width (< 300 ns) also determines the internal dead
time of the module.
5.3 CFT and CFRR mode
In the normal constant fraction mode the applied input signal is sensed for the amplitude by IC1 as
described above, but also routed to the front panel DELAY cable BNC connectors. The delayed
pulse is applied to the inverting input of the comparator IC2. The non delayed but attenuated signal
is applied to the non-inverting input of IC2. The attenuation is determined by the fraction module. The
difference signal between this inputs is a bipolar signal whose zero crossing is the time mark.
Theoretically the time mark for the bipolar signal is zero. Finite errors, such as small dc-offsets on
the input signal, the offset bias of the comparator, as well as the finite gain bandwidth of the device
can cause some time shift or walk in the normal case. With the front panel WALK ADJUST, by
monitoring the inspect signal one has the possibility to minimise the time walk. The optimum setting
has to be found experimentally. One logic output of IC2 is applied to gate IC5. Switch S-A is not
grounded in CFT operation. The outputs of IC3 and IC5 are applied to gate IC6. In normal operation
the first negative going pulse is provided from IC3. The
following pulse logic is identical as described
above. In the CFT operation switch S-B is grounded, the level at the D-input of the flip-flop (IC7) is
always logic LOW (-1.7V).
In cases where slower rise time pulses may cause poor timing performance, the CFRR mode locks
out and rejects those pulses which do not satisfy the THRESHOLD setting prior to the derived
constant fraction timing mark.
In the CFRR mode switch S-B is left open. The output signal of IC3 is processed through IC4 and
applied to the data input of the flip-flop IC7. Therefore output signals are only generated when the
threshold signal is prior to the derived timing mark of IC2. Inadvertent timing marks derived from the
leading edge discriminator switching late are blocked.
12
F
ComTec GmbH
