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9

Quick Start

•  Turn the length knob to “8”. Turn the chance 

knob fully counterclockwise. Move all switch-
es to the centre position.

•  Patch a signal crossing 1V to the clock input. 

Move the clock switch to the left position.  
Observe the clock output at Bus1. 

•  Move the clock switch to the right position. 

Observe the clock output at Bus2.

•  Experiment with moving the clock division 

switches to the right or left position. Clock 
divisions are mixed via OR gates at Bus1 or 
Bus2 according to the switch positions. The 
shift register is clocked by the signal at Bus1.

•  Patch any signal to the Data input and send a 

clock division to Bus1 by moving its switch to 
the left position. Data will now enter the shift 
register according to the signal flow diagram. 
With chance fully counter-clockwise; an XOR 
of the data input and the loop point.

•  Patch the 3-bit or 8-bit output to the fm input 

of an oscillator. Observe the oscillator pitch 
changing according to the data pattern. 

•  Use the write switch to overwrite high or low 

data into the shift register.

•  Turn the chance knob fully clockwise to lock 

the pattern in a loop.

•  Press the direction button or use a gate signal 

to reverse the direction of the pattern. 

•  Turn the length knob or patch a cv to change 

the length of the looping pattern.

•  Turn the chance knob or patch a cv to affect 

the chance of data coming from the data  
input, the noise source, or the loop point set 
by the length and direction parameters.

Rung Divisions combines a universal shift regis-
ter, a “divide by n” pulse divider, analogue noise, 
and several logic and binary operations. These 
functions synthesise an array of predictable and 
unpredictable digital signals at arbitrary time 
scale.

Rung Divisions’ primary use is as a complex 
polyrhythmic gate generator that drives a chaot-
ic / pseudo random / looping stepped cv pattern 
generator, with voltage control over the pattern 
“direction”, length, and chance of the pattern 
looping. The combination of these features can 
be used to generate auditory illusions similar to 
a stroboscopic effect – like the visual aliasing of 
a wheel that appears to stand still and reverse 
direction at speed. Rung Divisions is designed 
with solid state & discrete logic blocks to work at 
frequencies between 0–40kHz.

Rung Divisions needs Clock and Data inputs to 
function, these inputs can be any signal that 
crosses 1V. The Data input can be taken from the 
built in Noise source or the clock division out-
puts. The clock divisions are mixed via OR gates 
at Bus1 and Bus2, Bus1 clocks the Universal Shift 
Register. The Data input passes through an XOR 
gate, the second input for this gate is derived 
from a complex logic block involving the chance, 
length, and direction parameters. The Universal 
Shift Register is encoded to 1-Bit, 3-Bit, and 
8-Bit outputs, the 3-Bit and 8-Bit outputs are 
reverse-encoded for palindromic movement. 
Feedback to the Clock and Data signal sources 
adds another layer of complexity to the possible 
signals generated via these parameters. 

/N PULSE DIVIDER

CLOCK INPUT

RESET INPUT

LENGTH CV

DIRECTION CV

DIRECTION &

LENGTH LOGIC

UNIVERSAL SHIFT REGISTER

3-BIT

1-BIT

TWO-WAY SWITCHED GATE BUS

BUS2

BUS1

8-BIT

8-BIT DAC

BITS 1-8

BITS 1-3

BIT-1

3-BIT DAC

XOR GATE

CHANCE LOGIC

DATA INPUT

CHANCE CV

DATA SWITCH

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Signal Flow Diagram

Fig. 5: Signal Flow

Содержание Rung Divisions

Страница 1: ...RUNG DIVISIONS Fancyyyyy User Manual...

Страница 2: ...nts Introduction 3 Panel Layout and Technical Specification 4 Clock Division 5 Bus Outputs 6 Universal Shift Register 7 Output Encoding 8 Signal Flow 9 Installation and Calibration 10 Expanders 11 Lim...

Страница 3: ...with the ability to extract lower fre quency CV signals from audio rate clock sources A strength of the Benjolin is how it behaves across the threshold of audio and sub audio rates the features of Run...

Страница 4: ...input Chance control and CV input Data input and data write switch Bus switches Clock divider Clock and Reset inputs Clock divider and Bus1 Bus 2 outputs 1 Bit 3 Bit 8 Bit outputs Panel Layout Technic...

Страница 5: ...all outputs The clock dividers can run at any frequency between 0 40kHz they can be used to generate poly rhythms and interrelated clock signals or as sub oscillator sub harmonic genera tors at audio...

Страница 6: ...plication factor 2 4 or 3 6 for example will have no effect The Bus outputs also share the pulse width of the incoming clock and can generate PWM sub harmonics at audio rates Organ like tones are also...

Страница 7: ...this is to send a low frequency clock in to Rung Divisions set the clock switch to the left position to send it to Bus1 and clock the reg ister set length to 8 set chance fully clockwise and push the...

Страница 8: ...d work well with further quantisation Due to the extensive CV over the shift regis ter parameters at audio rate the encoded outputs make for a flexible and comprehen sive noise oscillator with as good...

Страница 9: ...ate discrete logic blocks to work at frequencies between 0 40kHz Rung Divisions needs Clock and Data inputs to function these inputs can be any signal that crosses 1V The Data input can be taken from...

Страница 10: ...reversibly damage the module The power header has reverse power protection and should be installed with the red stripe facing down aligned with the mark on the rear PCB The trim pot at the bottom of t...

Страница 11: ...Fancyyyyy 11 Expanders Coming soon...

Страница 12: ...damage arising for mistreatment ie dropping submerging etc Damage caused by incorrect power connections Overexposure to heat or direct sunlight Damage caused by inappropriate or misuse including physi...

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