Fancyyyyy Rung Divisions, Руководство пользователя

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Fancyyyyy
7
Universal Shift
Register
The CV outputs from Rung
Divisions are generated via a
Universal Shift Register. The
Universal Shift Register takes
its clock from the signal at
Bus1. The Data input is derived
from the front panel settings:
The loop point (length) of the
shift register can be changed
under CV, the CV input is
added to the knob position.
The read direction of the shift
register can be changed by
pressing the front panel but-
ton or sending a gate into the
direction input.
The chance of new data enter-
ing the shift register can be
controlled under CV, when the
knob is fully clockwise the
pattern loops, in the counter
clockwise position the data
comes from an XOR of the
front panel data jack and the
loop point set by length and
direction. The mid position is a
noisy interference between
the data jack and loop point.
A shift register is a primitive kind of digital
memory; the first bit of memory in the regis-
ter checks its data input every time its clock
signal goes high, if the data input is also high
at this time, then the first bit of memory
stores this high state and waits until the next
time the clock goes high. At the next clock
high state, the first bit passes it’s state onto
the next bit in the chain and checks the data
input again to update it’s own state. In this
way, bits of information are passed down the
register. A simple way to visualise this is to
send a low frequency clock in to Rung
Divisions, set the clock switch to the left
position to send it to Bus1 and clock the reg-
ister, set length to “8”, set chance fully
clockwise, and push the write switch high
momentarily. You will see the first led light up
of the shift register status display, and the
led will shift to the right (or left, depending on
the direction setting) at each clock pulse.
When not using the write switch, the data
input for the first bit of Rung Divisions is
derived from a relatively complex logical
block with parameters taken from the
chance, length, and direction controls.
These two controls set if the data should loop
from a loop point, or take new data from the
data input on the front panel. All incoming
data from the front panel is passed through
an XOR gate - this means that the shift regis-
ter is inherently unstable when data is
present at the front panel. Please see fig. 5
signal flow diagram on p.9.
Note that the length parameter changes the
loop point regardless of the current state of
data in the shift register, it is possible to lose
a pattern in situations where data has
passed the loop point and the length param-
eter is changed - for example if you have a
length 6 loop and change the loop point
when only bit 7 and 8 are high, those two bits
of data will be “lost” as they have already
passed the loop point.
It is possible to patch a voltage controlled
clock divider by looping a sequence, setting
1 bit of data high and using the 1-bit output to
clock a sample and hold to update the length
parameter at the start of each loop.