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20
AN-8026 / FEB301_FAN9611 / FAN9612 • Rev. 0.0.4
8.5.
Phase Management
Test Condition: Change
the output load to observe the phase shedding and adding.
Figure 21. Phase-Shedding
Figure 22. Zoom-In
Note:
9.
Figure 21 and Figure 22 show the phase-shedding waveforms. The duty cycle of the channel 1 gate drive signal
is doubled when the other channel gate drive signal is disabled to minimize the line current glitch.
Figure 23. Phase-Adding
Figure 24. Zoom-In
Note:
10. Figure 23 and Figure 24 show the phase-adding waveforms. The duty cycle of Channel 1 gate drive signal
becomes half just before the other channel gate drive signal is enabled to minimize the line current glitch.
Figure 25. Phase-Shedding and Line Current
Figure 26. Phase-Adding and Line Current
Note:
11. Figure 25 and Figure 26 show the sum of two-inductor current and line current for phase shedding and adding,
respectively. As shown, the phase management causes no visible change in the line current waveforms.
