FabiaTech Corporation
Bit 4: Clear to Send (CTS)
Bit 5: Data Set Ready (DSR)
Bit 6: Ring Indicator (RI)
Bit 7: Received Line Signal Detect (RSLD)
Divisor Latch (LS, MS)
LS
MS
Bit 0:
Bit 0
Bit 8
Bit 1:
Bit 1
Bit 9
Bit 2:
Bit 2
Bit 10
Bit 3:
Bit 3
Bit 11
Bit 4:
Bit 4
Bit 12
Bit 5:
Bit 5
Bit 13
Bit 6:
Bit 6
Bit 14
Bit 7:
Bit 7
Bit 15
Desired Baud
Rate
Divisor Used to Generate 16x
Clock
300 384
600 192
1200 96
1800 64
2400 48
3600 32
4800 24
9600 12
14400 8
19200 6
28800 4
38400 3
57600 2
115200 1
77
Содержание FX5653
Страница 15: ...FabiaTech Corporation g3 FX5622K1 Rack Mount 11 ...
Страница 35: ...FabiaTech Corporation Super IO Configuration This section describes the function of Super I O settings 31 ...
Страница 41: ...FabiaTech Corporation Chipset This section describes the configuration of the board s chipset features 37 ...
Страница 42: ...FabiaTech Corporation Host Bridge Host Bridge Parameters 38 ...
Страница 45: ...FabiaTech Corporation South Bridge South Bridge Parameters 41 ...
Страница 69: ...FabiaTech Corporation Exit extended function mode Mov dx 2eh Mov al aah Out dx al 65 ...
Страница 82: ...FabiaTech Corporation Appendix Dimension a FX5653 250 REF 50 REF 180 REF 78 ...
Страница 83: ...FabiaTech Corporation b FX5504K1 61 2 REF 118 REF 75 100 19 REF 7 75 100 75 REF 12 5 8 79 ...
Страница 84: ...FabiaTech Corporation c FX5501K1 278 REF 264 REF 58 REF 37 47 140 90 REF 8 10 80 ...
Страница 85: ...FabiaTech Corporation 81 d FX5622K1 455 REF 469 REF 480 REF 31 75 44 50 REF ...
