EVOC EC4-1812CLDNA, Руководство пользователя, Страница: 32 / 68

Appendix
­ 28 ­ EC4­1812CLDNA
data, read HST_STS status register in circulation; when bir[2]DEV_ERR is set to
1, indicating transmission error has occurred; when bir[1]INTR is set to 1,
indicating transmission complete and could implement next step.
3. Follow step 2 to modify other GPIO controlling register.
4. Read GPIO controlling register: enter Smbus I/O space, write 0xbf to HST_STS,
clear status bit, set bit[4:2] of HST_CNT register to 010, write 0x41 (read
command) to XMIL_SLAVE register, write GPIO controlling register 0x00 to
HST_CMD.
5. Start: set HST_CNT bir[6]START to 1, start to transmit address, command and
read HST_ST status register in circulation, when bir[2]DEV_ERR is set to 1,
indicating transmission error has occurred; when bir[1]INTR is set to 1,
indicating transmission completed. At that time, input register is to set the level
of input pin to DATA0 register and read DATA0 register to get the level of input
pin.
Set the I/O pin and high­low level according to the programming flow above.