EVOC EC4-1812CLDNA, Руководство пользователя, Страница: 31 / 68

Appendix
EC4­1812CLDNA ­ 27 ­
0x01­output port (Read/Write), when bit7~bit0 is 1, its corresponding pin is high level;
when bit7~bit0 is 0, it is low level.
0x02­Polarity Inversion (Read/Write), default value is 0x00, when bit7~bit0 is 1, level
reverse conversed.
0x03­Configuration (Read/Write), default value is 0xff, enable/disable output/input
function, when bit7~bit0 is 1, the output function of its corresponding pin is disabled
and input function is enabled; when bit7~bit0 is 0, the output function of its
corresponding pin is enabled and input function is disabled.
5 SMBUS registers
BAR+Offset 0x00: HST_STS status register:
BAR+Offset 0x02: HST_CNT controlling register
BAR+Offset 0x03: HST_CMD command register, Bit[7:0] used to select GPIO
controlling register;
BAR+Offset 0x04: XMIL_SLAVE address register, Bit[7:0] used to write in Slave
Address and read write bit;
BAR+Offset 0x05: DATA0: data register, used to store the receiving and sending data;
Program controlling flow:
1. Write GPIO controlling register: enter Smbus I/O space, write 0xbf to HST_STS
and clear status bit; set bit[4:2] of HST_CNT register to 010; write 0x40/042
(write command) to XMIL_SLAVE register, write GPIO controlling register
0x03 to HST_CMD,, write 0x0f to DATA0, modify the value of GPIO
controlling register to 0x0f; set GP1, 3, 5, 7 to input and GP2, 4, 6, 8, to output.
2. Start: set HST_CNT bir[6]START to 1, start to transmit address, command and