VULCAN Technical Manual
Detailed hardware description
© 2007 Eurotech Ltd Issue D
25
Watchdog timers
The IXP425 contains an internal WatchDog Timer (WDT), which may be used by
software applications to monitor inactivity. Timeout periods can be adjusted in steps of
15ns using a 32 bit counter register up to a maximum of 64 seconds. WDT can be
programmed to reset the processor or to generate interrupt when a timeout occurs.
Upon reset, the watchdog timer is disabled, and remains so until enabled by the
software.
For more information, please refer to either the Eurotech Operating System Technical
Manual or the IXP425 Developer’s Manual.
In addition, an external WD timer (MAX6369) is available. This is a programmable
watchdog timer that can be adjusted for timeout periods of 1ms, 10ms, 30ms, 100ms,
1s, 10s and 60s. The board is reset when timeout occurs. The MAX6369 WDT can be
programmed using the WD setup register provided within the CPLD. The register is
memory mapped and located on the expansion bus (CS5#). The WDT is disabled upon
reset, and remains so until enabled by the software.
The following table shows the WD setup register bit definitions:
Bits Description
7:5 Not
used.
4
PCI_RST#: When zero, resets PCI bus. Set to one if not used.
3
WDI: Watchdog Input. If WDI remains either high or low for the
duration of the watchdog timeout period (t
WD
), WDT triggers a reset
pulse. The internal watchdog timer clears whenever a reset pulse
is asserted or whenever WDI sees a rising or falling edge.
2:0
WDSET[2:0] - watchdog timeout period setup bits.
Hex Offset Address:
0x05000000
Reset Hex Value:
0x1B
Access:
Read/write
Bit 4 of WD setup register is not related to Watch Dog Timer. It is PCI bus reset
bit. When writing to this register make sure that you mask PCI_RST# bit.