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11 CPU-1450 SPM block diagram architecture
Intel 82801 ICH2 and System Power States
Table 1 shows the power states defined for ICH2-based platforms, the state names generally match the
corresponding ACPI states, the hardware implementation of the CPU-1450 assembly does not support the
greyed areas listed in the following table:
State/Sub-states Legacy Name / Description
G0/S0/C0
Full On: Processor operating. Individual devices may be shut down to save power. The different processor
operating levels are defined by Cx states, as shown in Table 4: Transitions Rules for ICH2 Within the C0 state, the
ICH2 can throttle the STPCLK# signal to reduce power consumption.
G0/S0/C1
Auto-Halt: The processor has executed an Auto-Halt instruction and is not executing code. The processor snoops
the bus and maintains cache coherency.
G0/S0/C2
Stop-Grant: The STPCLK# signal goes active to the processor. The processor performs a Stop-Grant cycle, halts
its instruction stream, and remains in that state until the STPCLK# signal goes inactive. In the Stop-Grant state,
the processor snoops the bus and maintains cache coherency.
G1/S1
Stop-Grant: Similar to G0/S0/C2 state. The ICH2 also has the option to assert the CPUSLP# signal to further
reduce processor power consumption.
G1/S3
Suspend-To-RAM (STR): The system context is maintained in system DRAM, but power is shut off to non-critical
circuits. Memory is retained and refreshes continue. All clocks stop except RTC clock.
G1/S4
Suspend-To-Disk (STD)
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: The context of the system is maintained on the disk. All power is then shut off to the
system except for the logic required to resume. Externally appears same as S5, but may have different wake
events.
G2/S5
Soft Off (SOFF): System context is not maintained. All power is shut off except for the logic required to restart. A
full boot is required when waking.
G3
Mechanical OFF (MOFF): System context not maintained. All power is shut off except for the RTC. No “Wake”
events are possible, because the system does not have any power. This state occurs if the user removes the
batteries, turns off a mechanical switch, or if the system power supply is at a level that is insufficient to power the
“waking” logic. When system power returns, transition depends on the state just prior to the entry to G3 and the
AFTERG3 bit in the GEN_PMCON3 register (D31:F0, offset A4).
Table 1. General Power States for Systems using ICH2
This table gives useful information, limited to the scope of this application note. For a more detailed
description refer to 82801 ICH2 Datasheet from Intel.
An0065. CPU-1450 Soft Power Management
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Considering that the standard O.S. management usually needs an ACPI hardware platform to manage the Suspend to
Disk functionality, also if the hardware allows the user to enter this mode, specific SW management, not provided by
Eurotech S.p.A., needs to be developed to fulfil this mode.