ETAS
Hardware Description
FETK-S2.1 - User’s Guide
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4.9
Pinless Triggering
4.9.1
Startup Handshake
The JTAG Data Communication (JDC) register is used to process the FETK
startup handshake. The ECU must ensure that all memory ECC initialization
has been completed prior to the start-up handshake.
For further information on ECC initialization, please refer to the microcontrol-
ler's reference manual.
4.9.2
FETK Trigger Generation
To generate triggers, the ECU software sets bits by writing the associated trig-
ger index in the "DTS_SEMAPHORE 1 and 2" register.
Each bit of the "DTS_SEMAPHORE" corresponds to an FETK hardware trigger.
Within the FETK’s configuration and/or A2L file, bit 0 corresponds to hardware
trigger 1 and bit 63 corresponds to hardware trigger 64.
The FETK periodically polls (reads) "DTS_SEMAPHORE" via JTAG. The polling
rate is configurable, with 50 µs default. The FETK then starts acquisition of
appropriate measurement data based on which bits of the register are set.
Active bits in "DTS_SEMAPHORE" are automatically cleared by the microcon-
troller when the register is read by FETK.
NOTE
The selective setting of trigger bits is accomplished in hardware by the micro-
controller and does not require a Read-Modify-Write sequence by the ECU
software.
NOTE
Only the index 0 to 63 corresponding to the first 64 triggers are supported by
the FETK-S2.1
