ETAS BR XETK-S1.0, Руководство пользователя

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ETAS Technical Data
BR_XETK-S1.0 - User’s Guide 42
7.9 DAP Timing Characteristics
The following diagrams show the timings the BR_XETK-S1.0 can process.
7.9.1 DAP Timing Diagram
Fig. 7-1 2-Pin DAP Timing Diagram
7.9.2 DAP Timing Parameter
NOTE
DAP timing parameters in this chapter refer to the DAP interface (CON2) of
the BR_XETK-S1.0. The DAP wiring to the ECU (ETAM2) must be taken
account additionally.
All timings are measured at a reference level of 1.5 V.
Parameter Symbol Value [ns] Comment
DAP0 Clock Period
(ETK --> Target) t
CLK
10 100 MHz DAP Clock Fre-
quency
20 50 MHz DAP Clock Fre-
quency
DAP1 Set-Up Time
(ETK --> Target) t
SU
4
DAP1 Hold Time
(ETK --> Target) t
H
2
DAP1 Clock-to-Out Time
(Target --> ETK) t
CO
~ Undetermined, ETK auto-
matically determines
optimum sampling point
DAP1 Valid Window
(Target --> ETK) t
Valid
8
DAP0_(ETK)
DAP1, DAP2_(ETK)
DAP1, DAP2_(ECU)
t
SU
t
H
t
CLK
t
CO
t
Valid