Espressif Systems ESP8684 Series, Руководство по проектированию аппаратного обеспечения, Страница: 11 / 28

2 Schematic Checklist
subject to the actual antenna and PCB layout. Figure 7 shows the RF matching schematic.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
The values of C8, L2 and C9
vary with the actual PCB board.
The values of C1 and C2 vary with
the selection of the crystal.
The value of R1 varies with the actual
PCB board.
ESP8684-MINI-1(pin-out)
NC: No component.
ESP8684H2
ESP8684H1
ESP8684H4
CHIP_EN
GPIO4
GPIO5
GPIO6
U0RXD
ANT
GPIO0
GPIO1
GPIO2
GPIO3
RF_ANT
U0TXD
GPIO2
GPIO3
CHIP_EN
G
P
IO
1
G
P
IO
0
G
P
IO
1
0
G
P
IO
6
G
P
IO
7
G
P
IO
8
G
P
IO
9
GPIO18
U0RXD
U0TXD
G
P
IO
4
G
P
IO
5
GPIO7
GPIO8
GPIO9
GPIO10
GPIO18
GND
VDD33
GND
GND GND GND
GND GND
GND
VDD33
GND GND GND
VDD33
VDD33
GND
GND
GND
GND GND
VDD33
GND
GND
Title
Size Page Name R e v
Date: Sheet o f
Confidential and Proprietary
<02_ESP8684-MINI-1> V1.0
ESP8684-MINI-1
A4
2 2 Friday, October 29, 2021
Title
Size Page Name R e v
Date: Sheet o f
Confidential and Proprietary
<02_ESP8684-MINI-1> V1.0
ESP8684-MINI-1
A4
2 2 Friday, October 29, 2021
Title
Size Page Name R e v
Date: Sheet o f
Confidential and Proprietary
<02_ESP8684-MINI-1> V1.0
ESP8684-MINI-1
A4
2 2 Friday, October 29, 2021
C1
TBD
R
1
0
(1
%
)
R2 499(1%)
Y1
40MHz
X
IN
1
G
N
D
2
X
O
U
T
3
G
N
D
4
L1 2.0nH(0.1nH)
C9
TBD
U2
ANT
1
VDDA3P3
2
VDDA3P3
3
GPIO0
4
GPIO1
5
GPIO2
6
C
H
IP
_
E
N
7
M
T
M
S
9
M
T
D
I
1
0
V
D
D
3
P
3
_
R
T
C
1
1
M
T
C
K
1
2
MTDO
13
GPIO8
14
GPIO9
15
GPIO10
16
VDD3P3_CPU
17
U
0
R
X
D
1
9
U
0
T
X
D
2
0
X
T
A
L
_
N
2
2
X
T
A
L
_
P
2
3
G
N
D
2
5
G
P
IO
3
8
V
D
D
A
2
4
V
D
D
A
2
1
GPIO18
18
C6
0.1uF/6.3V(10%)
D1
ESD
C3
1uF/6.3V(20%)
C4
10nF/6.3V(10%)
C10
0.1uF/6.3V(10%)
C7
0.1uF/6.3V(10%)
ANT1
PCB_ANT
1
2
U3
ESP8684-MINI-1
GND
1
3V3
3
IO
9
2
3
NC
4
IO2
5
IO3
6
NC
7
NC
9
NC
10
N
C
1
5
IO
1
0
1
6
N
C
1
7
IO
4
1
8
IO
5
1
9
NC
32
TXD0
31
RXD0
30
NC
34
NC
33
IO18
26
NC
29
NC
28
NC
27
IO
7
2
1
IO
8
2
2
IO
0
1
2
IO
1
1
3
GND
52
IO
6
2
0
NC
35
N
C
2
4
E
P
A
D
4
9
GND
2
GND
53
GND
51
GND
50
EN
8
G
N
D
3
6
G
N
D
3
7
G
N
D
3
8
G
N
D
3
9
G
N
D
4
0
G
N
D
4
1
G
N
D
4
2
G
N
D
4
3
G
N
D
4
4
G
N
D
4
5
G
N
D
4
6
G
N
D
4
7
G
N
D
4
8
G
N
D
1
4
GND
11
NC
25
C2
TBD
C8
TBD
C12
0.1uF/6.3V(10%)
L2
TBD
C5
10uF/6.3V(20%)
Figure 7: Schematic for RF Matching
2.6 UART
It is recommended to connect a 499 Ω series resistor to the U0TXD line in order to suppress the 80 MHz
harmonics.
2.7 ADC
It is recommended to add a 0.1
µ
F filter capacitor between pins and ground when using the ADC function.
2.8 Strapping Pins
Note:
The content below is excerpted from Section Strapping Pins in ESP8684 Series Datasheet .
ESP8684 series has two strapping pins:
• GPIO8
• GPIO9
Software can read the values of GPIO8 and GPIO9 from GPIO_STRAPPING field in GPIO_STRAP_REG register.
For register description, please refer to Section GPIO Matrix Register Summary in
ESP8684 Technical Reference Manual .
During the chip’s power-on reset, RTC watchdog reset, and brownout reset, the latches of the strapping pins
sample the voltage level as strapping bits of ”0” or ”1”, and hold these bits until the chip is powered down or shut
down.
By default, GPIO9 is connected to the internal weak pull-up resistor. If GPIO9 is not connected or connected to
an external high-impedance circuit, the latched bit value will be ”1”
To change the strapping bit values, you can apply the external pull-down/pull-up resistances, or use the host
MCU’s GPIOs to control the voltage level of these pins when powering on ESP8684.
After reset, the strapping pins work as normal-function pins.
Table 2 lists detailed booting configurations of the strapping pins.
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ESP8684 Series Hardware Design Guidelines v1.1