2
Schematic Checklist
2.5 RF
In your circuit design, please add a
π
-matching network for antenna matching, preferably a CLC network.
5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A
A
NC: No component.
The values of C8, L2 and C9
vary with the actual PCB board.
The values of C1 and C2 vary with
the selection of the crystal.
The value of R1 varies with the actual
PCB board.
GPIO19
CHIP_EN
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
U0RXD
GPIO18
LNA_IN
GPIO9
GPIO10
GPIO0
GPIO1
SPICS0
SPID
SPIQ
SPICLK
SPIWP
SPIHD
GPIO2
GPIO3
RF_ANT
U0TXD
SPICLK
SPICS0
SPIHD
SPIWP
SPID
SPIQ
GND
VDD33
GND
GND
GND
GND
GND
GND
GND
GND
VDD33
GND
GND
GND
VDD33
VDD_SPI
VDD33
GND
VDD_SPI
GND
GND
GND
GND
C1
TBD
C9
TBD
U3
FLASH-3V3
/CS
1
DO
2
/WP
3
G
N
D
4
DI
5
CLK
6
/HOLD
7
V
C
C
8
R4
0
R7
0
R6
0
C12
0.1uF
R
1
0
ANT1
PCB_ANT
1
2
R5
0
C10
0.1uF
C3
1uF
R2
499
R3
0
L1
2.0nH
C2
TBD
C8
TBD
C6
0.1uF
L2
TBD
C5
10uF
C4
100pF
C7
0.1uF
C11
1uF
U2
ESP32-C3
LNA_IN
1
VDD3P3
2
VDD3P3
3
XTAL_32K_P
4
XTAL_32K_N
5
GPIO2
6
CHIP_EN
7
M
T
M
S
9
M
T
D
I
1
0
V
D
D
3
P
3
_
R
T
C
1
1
M
T
C
K
1
2
M
T
D
O
1
3
G
P
IO
8
1
4
G
P
IO
9
1
5
G
P
IO
1
0
1
6
VDD3P3_CPU
17
VDD_SPI
18
SPIHD
19
SPIWP
20
SPICS0
21
SPICLK
22
SPID
23
SPIQ
24
U
0
R
X
D
2
7
U
0
T
X
D
2
8
X
T
A
L
_
N
2
9
X
T
A
L
_
P
3
0
G
N
D
3
3
GPIO3
8
V
D
D
A
3
2
V
D
D
A
3
1
G
P
IO
1
9
2
6
G
P
IO
1
8
2
5
U1
40MHz(±10ppm)
X
IN
1
G
N
D
2
X
O
U
T
3
G
N
D
4
R8
10K
Figure 9: ESP32C3 Family RF Matching Schematic
Note:
The parameters of the components in the matching network are subject to the actual antenna and PCB layout.
2.6 UART
You need to connect a 499
Ω
resistor to the U0TXD line to suppress the 80 MHz harmonics.
2.7 ADC
It is recommended to add a 0.1
µ
F filter capacitor between pins and ground when using the ADC function.
Please note that ADC2 is not factory-calibrated. We recommend using ADC1.
2.8 Strapping Pins
Note:
The content below is excerpted from Section Strapping Pins in
.
ESP32-C3 family has three strapping pins:
• GPIO2
• GPIO8
• GPIO9
Software can read the values of GPIO2, GPIO8 and GPIO9 from GPIO_STRAPPING field in GPIO_STRAP_REG
register. For register description, please refer to Section GPIO Matrix Register Summary in
ESP32-C3 Technical Reference Manual
During the chip’s system reset, the latches of the strapping pins sample the voltage level as strapping bits of ”0”
or ”1”, and hold these bits until the chip is powered down or shut down.
Types of system reset include:
Espressif Systems
11
ESP32-C3 Family Hardware Design Guidelines V1.0