ESMT F25L04PA Series, Руководство пользователя

Страница: 23 / 33

ESMT
F25L04PA (2D)
Elite Semiconductor Memory Technology Inc.
Publication D ate: Aug. 2012
Revision: 1.4 23/33
Table 10: CAPACITANCE (T
A
= 25°C, f=1 MHz, other pins open)
Parameter Description Test Condition Maximum
C
OUT
1
Output Pin Capacitance V
OUT
= 0V 8 pF
C
IN
1
Input Capacitance V
IN
= 0V 6 pF
Note 1: This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
Table 11: AC OPERATING CHARACTERISTICS
Normal 33MHz Fast 50 MHz Fast 86 MHz Fast 100 MHz
Symbol Parameter
Min Max Min Max Min Max Min Max
Unit
F
CLK
Serial Clock Frequency 33 50 86 100 MHz
T
SCKH
2
Serial Clock High Time 13 9 5 4 ns
T
SCKL
2
Serial Clock Low Time 13 9 5 4 ns
T
CLCH
Clock Rise Time (Slew Rate) 0.1 0.1 0.1 0.1 V/ns
T
CHCL
Clock Fall Time (Slew Rate) 0.1 0.1 0.1 0.1 V/ns
T
CES
1
CE Active Setup Time
5 5 5 5 ns
T
CEH
1
CE Active Hold Time
5 5 5 5 ns
T
CHS
1
CE Not Active Setup Time
5 5 5 5 ns
T
CHH
1
CE Not Active Hold Time
5 5 5 5 ns
T
CPH
CE High Time
100 100 100 100 ns
T
CHZ
CE High to High-Z Output
6 6 6 6 ns
T
CLZ
SCK Low to Low-Z Output 0 0 0 0 ns
T
DS
Data In Setup Time 2 2 2 2 ns
T
DH
Data In Hold Time 5 5 5 5 ns
T
HLS
HOLD Low Setup Time
5 5 5 5 ns
T
HHS
HOLD High Setup Time
5 5 5 5 ns