background image

November 2007

  Rev 2

1/9

UM0453

User manual

M29W128GH/L Flash memory VHDL model v1.1

1 Introduction

This user manual describes the VHDL (VHSIC hardware description language) v1.1 
behavioral model for the M29W128GH and M29W128GL Flash memory devices. 

Organization of the VHDL model delivery package

The VHDL model delivery package is organized into a main directory, named 

ST_M29W128G_V11.zip

, containing six subdirectories with their related files (see 

Figure 1

).

code subdirectory: contains the code

lib subdirectory: contains library source files

sim subdirectory: contains the simulation initialization files

stim subdirectory: contains the stimuli files used for simulation

top subdirectory: contains the testbench file used for simulation

doc subdirectory: contains the application note for the model

Figure 1.

Package architecture 

Note:

See the readme.txt file for the complete list of files contained in each folder.

Ai14413b

ST_M29W128G_V11.zip

doc

sim 

code

stim

readme.txt
run_ncsim

m29w128g.vhd   VHDL model

M29W128G_V1.1_UserManual.pdf

memory_file
CFImemory_file
NVMP_file

Autoselect.vhd
BlockErase.vhd
CFIAutoSelect.vhd
ChipErase.vhd
BufferProgram.vhd
EraseProgramSuspend.vhd
EraseSuspend.vhd
ExtendedBlock.vhd
Program.vhd
ProgramSuspend.vhd
ReadCFI.vhd
SpecialBusOp.vhd
UnlockBypass.vhd
VPPBypass.vhd

top

TestBench.vhd tesbench file        

lib

block_data.vhd
extended_memory.vhd
generic_data.vhd
protection_group.vhd
string_util.vhd
utility_pack.vhd

www.st.com

Содержание M29W128GH

Страница 1: ...ains the stimuli files used for simulation top subdirectory contains the testbench file used for simulation doc subdirectory contains the application note for the model Figure 1 Package architecture Note See the readme txt file for the complete list of files contained in each folder Ai14413b ST_M29W128G_V11 zip doc sim code stim readme txt run_ncsim m29w128g vhd VHDL model M29W128G_V1 1_UserManual...

Страница 2: ...scription 4 3 VHDL behavioral model 5 3 1 Model libraries 5 3 2 Testbench and stimuli files 5 4 Simulation guidelines 6 4 1 Launching a simulation 6 4 2 Simulation timings 6 4 3 memory_file file format 6 5 VHDL types used in model ports 7 6 Revision history 8 ...

Страница 3: ...UM0453 List of tables 3 9 List of tables Table 1 Simulation timings 6 Table 2 Model ports for the M29W128G devices 7 Table 3 Document revision history 8 ...

Страница 4: ... signals control the bus operation of the memory They allow simple connection to most microprocessors often without additional logic The M29W128GH and M29W128GL support asynchronous random read and page read from all blocks of the memory array The devices also feature a write to buffer program capability that improves the programming throughput by programming in one instance a buffer of 32 words 6...

Страница 5: ... 1 string_util vhd This library contains the utilities used for string management 2 generic_data vhd This library contains generic constants 3 utility_pack vhd This library contains some generic procedures 4 protection_group vhd This library contains functions for protection group management 5 extended_memory vhd This library contains generic constants for extended memory management 6 timing_data ...

Страница 6: ..._file located in the sim subdirectory must be hex_first_address hex_data For example 07FFFF 7FFF The file name must be written to the entity file this filename path cannot be empty generic memoryfile string path filename If the initialization file is not provided all the memory bits are set to 1 and the whole array is erased Similarly the CFImemory_file file loads the model CFI area of the M29W128...

Страница 7: ... A22 Standard logic 22 down to 0 Address inputs DQ0 DQ14 Standard logic 14 down to 0 Data input output Dq15A 1 Standard logic Data input output or address input BYTE Standard logic Byte word organization select E_N Standard logic Chip Enable G_N Standard logic Output Enable W_N Standard logic Write Enable RP_N Real Reset block temporary unprotect VPP WP_N Real VPP Write protect RB Standard logic R...

Страница 8: ... history Date Revision Changes 10 Sep 2007 1 Initial release 20 Nov 2007 2 Updated the document to reflect increment in software version 1 0 to 1 1 In Table 1 Simulation timings added the unit column changed the Chip erase times from 80 800 10 6 to 40 400 10 6 respectively ...

Страница 9: ...NTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE ST PRODUCTS ARE NOT RECOMMENDED AUTHORIZED OR WARRANTED FOR USE IN MILITARY AIR CRAFT SPACE LIFE SAVING OR LIFE SUSTAINING APPLICATIONS ...

Отзывы: