ESI VideoBridge 2150, Руководство по обслуживанию

Страница: 186 / 332

3 . 4 . 2
S ta ndard
Commu n i ca t i o n s Bus
W h e n the C P U a d d re s s e s a d e v i c e on t he ou tpu t s i de ( E XTERNAL ) of t he
C P U b u f f e rs , i t a l s o n e e d s to be s i n g le d ou t ( S E L E C T E D ) be f ore i t c a n
s p e a k o r b e s p o k e n t o . T h e r e a r e a n u m b e r o f l i n e s , c a l l e d t h e
s ta n da rd ( S TD ) bus , t ha t a re d e d i c a t e d t o con vey i ng
a dd r e s s
i n forma t i on , con t ro l s i g na l s , a n d da ta t o a n d f r om t h e se E XTERNAL
devi ces . T he STD bus h a s s i x l o c a t i on s f o r p l ugg i ng i n mea s u reme n t
a n d I / O d e d i c a t e d d e v i c e s . S t a n d a r d b u s s i g n a l s a n d c a r d e d g e
c o n ne c t i on s a r e i de n t i f i e d i n T a b l e 3 - 1 . De v i c e s tha t a re se r v i ced by
t h e STD b u s a re :
LOG I C
POWE R
B U S
DATA
B U S
A D D R E S S
BUS
CON TROL
BUS
POWER
BUS
1 . D i g i ta l a n d A n a l o g Me a su r e me n t c i r c u i t a s sem b l i e s .
2 . GP I B c i r c u i t a s s e mb l y ( op t i ona l ) .
3 . R S 2 3 2 I n t e r f a ce c i r c u i t a s se m b l y ( op t i ona l on 2 1 5 0 ) .
4 . C a s s e t t e tape i n t e r f a c e ( M ode l 2 1 6 0 o n l y ) .
Tab.1e 3 - .1 . S ta ndard Bus
S i g na l s and C a rd Edge
Conne c t i on s
PI N
M N EM O N I C
S I G N A L
D E S C R I PT I O N P I N M N EM O N I C
S I G NA L
D ESCRI PTI O N
F LOW F LOW
1
+
5 V I n
+ 5 Vo l � DC (Bussed)
2 + 5 V
I n + 5 Vo l � DC (Bussed)
3 G N D I n
D i g i ta l Ground (Bussed) 4 G N D
I n
Dig i to
I
Ground (Bussed)
5 - 5V In - 5 Vo l � DC
6 - 5 V I n - 5 Vo l � D C
7 D3 In/Out Low Order Data Bus
8
D7 In/Out
H i gh O rder Data Bus
9 D 2
In/Out Low Order Data Bus 1 0
D6
In/Out H igh O rder Data Bus
1 1 D l In/Out Low O rder Data Bus
1 2
D5 I n/O ut
H i gh O rder Data Bus
1 3 DO
I n/Ou t Low Order Data Bus 14
D4
In/Out
H i gh O rder Data Bus
1 5
A 7 Out
Low Order Address Bus 1 6 A 1 5 Out H i gh O rder Address Bus
1 7 A6
Out
Low Order Address Bus
1 8 A 1 4 Out
H i gh O rder A ddress Bus
1 9 A5 Out
Low Order Address Bus 20 A 1 3 O ut H igh O rder Address Bus
2 1
A4 Out
Low Order Address Bus
22 A 1 2
Out H i g h O rder Address Bus
23 A3 Out
Low Order Address Bus 24 A l l Out H igh O rder A ddress Bus
25
A 2 O u t
Low Order Address Bus
26
A l 0 Out H i gh O rder A ddress Bus
27 A l O ut
Low Order Address Bus 28 A 9 Out
H i gh Order A ddress Bus
29 AO Out
Low Order Address Bus 30 A8 Out H i gh O rder Address Bus
3 1 WR* Out Wri te to Memory or I/O 3 2 RD* Out Read to Memory or I/O
33
1 0 RQ*
Out I /O Address Select
34 M E M RQ* Out Memory Address Se l ect
35 1 0 0 X P* In/O ut I /O Expansion 36 M EM E X* In/Out Memory Expans ion
37 REFRE SH* Out Refresh Timing 38
M C SYNC* NA C PU Machine Cyc l e Sync
39 S TA TUS 1* Out CPU Status (Z80-M 1) 40 SA TUS
0"
Out CPU S tatus
4 1 BUSAK* Out Bus Acknowledge 42
BUS RQ* In Bus Request
43 I NTAK*
Out
I nterrupt Acknowl edge I N TRQ* In I nterrupt Request
45 WA I TRQ* In Wa i t Request 46
NM I RQ*
I n
Non-M oskab l e I n terrupt
4 7 S YS RE S ET* Out System Reset
48
PBRES ET* I n Push Button Reset
49
C LO C K*
Out
Clock Pro cessor 4 . 0 M H z
5 0 CN T R L* I n C P U C lock 3 . 84 M H z
5 1 PCO* Out Priori ty Cha i n Out 52 PCI* I n Priori ty Cho i n I n
5 3 AUX G N D I n A U X Ground (Bussed) 54 AUX G N D I n AUX G round (Bussed)
55 AUX
+
V In A U X Pos i tive
(+
1 2 Vo l ts D C ) 5 6 AUX - V I n AUX N egat i ve (- 1 2 V o l ts D C )
* Low
Leve l Act i ve I nd i cator
e l s l i
3 - 2 2
2 1 5 0/ 2 1 6 0 9 /8 5
•