Technical Data
5.2 PCI Bus
Host bus
PCI-Bus according to PCI Local Bus Specification 2.2
PMC specification
IEEE Standard 1386.1-2001
PCI bus master capability
yes
PCI-data bus
32 bit
PCI bus clock rate
33 MHz and 66 MHz
Signalling environment
Universal board,
3.3 V signal level and 5 V signal level
Microprocessor
optional: 32-bit microprocessor in FPGA
Memory
Block RAM: 72 KB
optional DRAM: 64 MB
Interrupt
interrupt signal INT A
Connectors
P11 (Pn1), P12 (Pn2), P14 (Pn4)
according to IEEE Standard P1386.1-2001
PMC-CAN/400-4
Hardware Manual • Doc. No.: C.2047.21 / Rev. 1.3
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