4. History Data Details
4.1.8
IDE: Multi Word DMA (H->D)
Refer to “4.1.7 IDE: Multi Word DMA (D->H)”.
4.1.9
IDE: Ultra DMA (D->H)
This history entry is recorded when Ultra DMA format data transfer starts. If “IDE:
INTRQ” or “IDE: CRC error” do not appear after the history entry, there may be a problem
with signal quality or in the signal connections shown below.
•
DIOW-, DIOR-, DMARQ, DMACK -, IORDY
4.1.10 IDE: Ultra DMA (H->D)
Refer to “4.1.9 IDE: Ultra DMA (D->H)”.
4.1.11 IDE: CRC error
This history entry is recorded when a CRC error is detected during Ultra DMA format data
transfers. If this history entry appears, there may be a problem with signal quality or in the
signal connections shown below.
•
DD0 to DD15
4.1.12 IDE:
INTRQ
This history entry is recorded in spite of the Device Control register nIEN bit when the
command issued by the main CPU has finished executing and the status register details
have been updated. If the main CPU cannot detect INTRQ even when this history entry
appears while the Device Control register nIEN bit is 0, there may be a problem with signal
quality or in the signal connection shown below.
•
INTRQ
Note that this history entry is not recorded when the following commands, for which
the ATA/ATAPI standards specify INTRQ is not to be asserted, terminate normally.
¾
IDENTIFY DEVICE
¾
IDENTIFY PACKET DEVICE
¾
READ SECTOR (S)
¾
READ SECTOR (S) EXT
¾
READ MULTIPLE
¾
READ MULTIPLE EXT
8
EPSON
S1R72U16 Development Support
Manual (Rev.2.00)
