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S1R72104 Technical Manual

10

EPSON

Rev.1.1

7.3 Detailed Description of Each Register

7.3.1 Main Interrupt Status (MAININT) R/W

When the IC interrupted CPU, the CPU first reads this register for processing the interruption to get to know
which interrupt status register is the factor.
After reading this register, the CPU reads the interrupt status register corresponding to each bit to find out the
bit that is the source of interrupt, and processes the interruption appropriately.    Then it writes the values read to
the interrupt status registers corresponding to each bit, then clearing the bits.
If GOOD, SABT, or DTCMP bit is the interrupt source, the CPU writes the value read to clear the bits.    The
register has no need to clear directly any other bits.

7 6 5 4 3 2 1 0

GOOD SABT EXEC SCSI1 SCSI2 -

DTCMP ASCMP

00h

AUTO

SEQUENCE

COMPLETE

DMA

TRANSFER

COMPLETE

SCSI

INTERRUPT

STATUS

2

SCSI

INTERRUPT

STATUS

1

EXECUTING

SCSI

COMMAND

ABORTED

SCSI

COMMAND

SCSI

COMMAND

NORMAL

COMPLETE

BIT7 SCSI COMMAND NORMAL COMPLETE

This bit becomes HIGH if a SCSI control command closed normally.

BIT6 ABORTED SCSI COMMAND

This bit becomes HIGH if a control command was forced to terminate by Abort command issued.

BIT5 EXECUTING SCSI COMMAND

This bit is HIGH while a SCSI control command is under execution. This bit is not a factor causing interrupt to the

CPU, so HIGH of this bit causes no interruption. It is used to monitor the execution of SCSI control command.

BIT4 SCSI INTERRUPT STATUS 1

This bit becomes HIGH if any interrupt factor about the SCSI interface is shown on SCSIINT1 register.

BIT3 SCSI INTERRUPT STATUS 2

This bit becomes HIGH if any interrupt factor about the SCSI interface is shown on SCSIINT2 register.

BIT1 DMA TRANSFER COMPLETE

This bit becomes HIGH when DMA data transfer activated by DMACTL register ends.
It becomes HIGH also when the transfer is forced to terminate by “0” written in DTGO bit of DMACTL register.

It becomes HIGH also if a command is aborted by Abort_SCSI command or if a command under execution is aborted

by ATN assertion after DTGO bit of DMACTL register was set because DMA terminates.

BIT0 AUTO SEQUENCE COMPLETE

This bit becomes HIGH when AUTO1 or AUTO2 bit of SCSIMODE0(09h) is set and the command processing

specified is over.

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Содержание S1R72104

Страница 1: ...Technical Manual SCSI Interface Controller S1R72104 MF1529 01 ...

Страница 2: ...reover no license to any intellectual property rights is granted by implication or otherwise and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exch...

Страница 3: ... 2 directions 0F Tape reel FRONT 0G TCP BT 4 directions 0H TCP BD 4 directions 0J TCP SL 2 directions 0K TCP SR 2 directions 0L Tape reel LEFT 0M TCP ST 2 directions 0N TCP SD 2 directions 0P TCP ST 4 directions 0Q TCP SD 4 directions 0R Tape reel RIGHT 99 Specs not fixed Specifications Shape F QFP Model number Model name R Exclusive use controller Peripheral Product classification S1 Semiconducto...

Страница 4: ...SI Mode Select1 SCSIMODE1 R W 14 7 3 7 SCSI Control SCSICTL R W 14 7 3 8 SCSI Data SCSIDATA R W 15 7 3 9 Synchronize Transfer Mode SYNCMODE R W 15 7 3 10 SCSI Own ID OWNID R W 16 7 3 11 Source Destination ID SDID R W 16 7 3 12 Selection Timeout Counter SLTIME R W 16 7 3 13 FIFO Control FIFOCTL R W 16 7 3 14 FIFO Data FIFODATA R W 17 7 3 15 Non DMA Transfer Size NDMASIZ R W 17 7 3 16 SCSI Command C...

Страница 5: ...ISTICS 30 8 1 Absolute Maximum Ratings 30 8 2 Recommended operational conditions 30 8 3 DC Characteristics 30 8 4 AC Characteristics 33 8 4 1 CPU Interface 34 8 4 2 SCSI Interface 36 8 4 3 Port Interface 49 8 4 4 Others 53 9 EXAMPLES OF CONNECTION 56 10 EXTERNAL DIMENSIONS DRAWING 57 ...

Страница 6: ...ous Compatible with SCSI 3 FAST20 20Mbps synchronous Compatible with SCAM Lv 1 compatible with Lv 2 with firmware Automatic processing of phase control Built in single end driver Active negation I O mounted PORT Interface Connectable directly to an IDE ATA DMA port Operational also as a general purpose port Others Built in oscillation circuit 20MHz 22 5MHz 40MHz Built in PLL circuit 100 pin QFP 0 ...

Страница 7: ...uence control Command analysis and execution Phase control Parity GEN CHK FIFO 16Byte DMA control FIFO control Asynchro nous transfer control Synchronous transfer SCAM control XSRST XSATN XSDP XSBSY XSIO XSCD XSMSG XSSEL XSDB7 0 XSREQ XSACK Clock distribution CPU interface section Timing control Interrupt control Data MPX DMA control section Start up stop control Internal register CLKI XPLLPW V C ...

Страница 8: ... VSS 82 44 PD1 NC 83 43 PD14 XSDB6 84 42 PD0 HVDD 85 41 PD15 XSDB5 86 40 PDREQ VSS 87 39 XPWR XSDB4 88 38 XPRD HVDD 89 37 XPDACK XSDB3 90 36 VSS VSS 91 35 XCS XSDB2 92 34 XINT NC 93 33 XRESET HVDD 94 32 XRD XSDB1 95 31 XWR VSS 96 30 AD4 XSDB0 97 29 AD3 HVDD 98 28 AD2 NC 99 27 AD1 VSS 100 26 LVDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 LV DD EXCLK V SS OSCIN OSCOUT LV DD C...

Страница 9: ...od SCSI RST signal Drive capability 48mA 68 XSMSG I Ood SCSI MSG signal Drive capability 48mA 66 XSSEL I Ood SCSI SEL signal Drive capability 48mA 65 XSCD I Ood SCSI C D signal Drive capability 48mA 63 XSREQ Is Otr SCSI REQ signal Drive capability 48mA 61 XSIO I Ood SCSI I O signal Drive capability 48mA Port interface related matters 20 38 XPRD Is O Port lead signal Drive capability 3mA 39 XPWR Is...

Страница 10: ...esting connected to LOW GND usually 7 CLKSEL0 I Input clock selection LOW GND OSCIN HIGH LVDD EXCLK input 8 CLKSEL1 I System clock selection LOW GND PLL output HIGH LVDD Selecting signal of CLKSEL0 11 PLLCT0 I Dependent on PLL operation control pin input clock input on 3 3V level 12 PLLCT1 I Dependent on PLL operation control pin input clock input on 3 3V level 2 EXCLK I 5V level external clock in...

Страница 11: ...r to and from the port according to the timing specified by the PDREQ XPDACK signals 4 The port allows selection of bit width 8 or 16 5 The port interface allows selection of the master or slave function toward PDREQ XPDACK XPRD XPWR direction 6 4 DMA Control Circuit This is a block which controls the transfer between DMA port and FIFO in SCSI 2 block It has the following functions 1 It controls t...

Страница 12: ...MHz 22 5MHz 40MHz from the OSCIN pin No PLL circuit is used because the internal clock can get necessary clock if the oscillator section is oscillated at 40MHz or if 40MHz clock is input from EXCLK pin If EXCLK pin is used set OSCIN pin to LOW if OSCIN pin is used set EXCLK pin to LOW Make settings as shown below depending on the ways of use 1 LVDD 0 VSS If oscillator circuit is used If external c...

Страница 13: ...Bh SCSI Control SCSICTL 0Ch SCSI DATA SCSIDATA 0Dh SCSI Synchronous data transfer Mode SYNCMODE 0Eh SCSI Own ID OWNID 0Fh SCSI Source Destination ID SDID 10h SCSI Selection Timeout Counter SELTIME 11h SCSI FIFO Control FIFOCTL 12h SCSI FIFO Data FIFODATA 13h SCSI Non DMA Transfer Size NDMASIZE 14h SCSI Command COMMAND 15h Reserved 16h Reserved 17h DMA Control DMACTL 18h Reserved 19h Host Transfer ...

Страница 14: ...ATE3 RATE2 RATE1 RATE0 OFF3 OFF2 OFF1 OFF0 0Eh R W OWNID 00h OID2 OID1 OID0 0Fh R W SDID xxh SID2 SID1 SID0 DID2 DID1 DID0 10h R W SELTIME 00h ST7 ST6 ST5 ST4 ST3 ST2 ST1 ST0 11h R W FIFOCTL 01h FCLR FULL EMPTY 12h R W FIFODATA xxh FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0 13h R W NDMASIZE FFh NSZ7 NSZ6 NSZ5 NSZ4 NSZ3 NSZ2 NSZ1 NSZ0 14h R W COMMAND 00h CMD7 CMD6 CMD5 CMD4 CMD3 CMD2 CMD1 CMD0 15h 16h 17h R W...

Страница 15: ... HIGH if a SCSI control command closed normally BIT6 ABORTED SCSI COMMAND This bit becomes HIGH if a control command was forced to terminate by Abort command issued BIT5 EXECUTING SCSI COMMAND This bit is HIGH while a SCSI control command is under execution This bit is not a factor causing interrupt to the CPU so HIGH of this bit causes no interruption It is used to monitor the execution of SCSI c...

Страница 16: ...ID bit is asserted or Three or more ID bits are asserted BIT5 SELECTION TIME OUT This bit becomes HIGH if time out was detected during the selection or reselection phase BIT4 SCSI ATN ASSERTION DETECTED This bit becomes HIGH if SCSI ATN was asserted It is not set though in the sequence where SCSI ATN is asserted usually such as the message out phase subsequent to selection BIT3 BUS FREE DETECTED T...

Страница 17: ...r ends or that the counter overflows underflows BIT4 UNDEFIND GROUP COMMAND This bit becomes HIGH if SCSI command other than group 0 1 2 or 5 was received BIT3 COMMAND ERROR This bit becomes HIGH if an undefined SCSI control command was issued or a control command was issued during execution of another command BIT2 RESELECTED This bit becomes HIGH if any other device made re selection during execu...

Страница 18: ...was executed At the end of execution ASCMP interrupt occurs The bit is valid also in FIFO DMA mode AUTO BIT2 AUTO2 status message stop Executes automatically STS_MSG after DMA_DATA_IN OUT command was executed At the end of execution ASCMP interrupt occurs The bit setting is valid also in FIFO DMA mode When this bit is used EXECbit is not turned OFF even if ASCMP occurs Configure the firmware so th...

Страница 19: ... which have been received are checked Status 00h GOOD and message 00h COMMAND COMPLETE status 10h INTERMEDIATE GOOD and message 0Ah LINKED COMMAND COMPLETE and status 10h INTERMEDIATE GOOD and message 0Bh LINKED COMMAND COMPLETE WITH FLAG are sent automatically if LINK bit is LOW LINK bit is HIGH and FLAG bit is LOW and LINK and FLAG bits are both HIGH respectively BIT3 RESELECTION INHIBIT HIGH of...

Страница 20: ...f set for SCSI synchronous transfer 7 6 5 4 3 2 1 0 RATE3 RATE2 RATE1 RATE0 OFF3 OFF2 OFF1 OFF0 0Dh SYNCHRONOUS OFFSET SYNCHRONOUS TRANSFER RATE RATE3 0 ASSERT NEGATE PERIOD OFF3 0 OFFSET 0000 1T 1T 2T 0000 Asynchronous 0001 2T 1T 3T Note 1 0001 1 0010 2T 2T 4T 0010 2 0011 3T 2T 5T 0011 3 0100 3T 3T 6T 0100 4 0101 4T 3T 7T 0101 5 0110 4T 4T 8T 0110 6 0111 5T 4T 9T 0111 7 1000 5T 5T 10T 1000 8 1001...

Страница 21: ... 2 1 0 ST7 ST6 ST5 ST4 ST3 ST2 ST1 ST0 10h The time out delay value is calculated according to the following formula Delay value count value 215 T 2 Where T is internal clock cycle 40MHz The IC acts as follows if it detected time out Suspends to output ID bit Negates XSSEL 4000 T 2 about 200µs after such suspension and outputs selection time out interrupt No time out is detected if 0 is set to thi...

Страница 22: ...tus of FIFO Alternately it may first write data in FIFO and set HIGH in this bit and DTGO then make control with remaining data and FULL EMPTY Though CPU may not access FIFO reversely against the direction of transfer This bit is used together with SCSI command for DMA Data In Out Note that FIFO is cleared when SCSI phase is switched to the data phase if DMA Data In Out command was issued without ...

Страница 23: ...IGH Output to XINT is 1 0 BIT5 PORT SLAVE Decides the operation mode of the port 0 Master mode PDREQ input XPDACK XPRD XPWR output 1 Slave mode PDREQ output XPDACK XPRD XPWR input BIT3 PDREQ LEVEL Decides the operation mode of PDREQ signal 0 Positive logic 1 Negative logic BIT2 SWAP PORT INTERFACE BUS Swaps the higher 8 bits with lower ones when the port interface is used with 16 bit width 0 Lower...

Страница 24: ...ransferred PD7 to 0 is used if the last data to be transferred is not a word but a byte SWAP 1 PD15 to 8 is transferred to and from SCSI block first If ODS 1 PD15 to 8 is discarded when the first one word is transferred and only PD7 to 0 is transferred PD15 to 8 is used if the last data to be transferred is not a word but a byte BUS8 1 Only PD7 0 is used for transfer PD15 to 8 is used for Input mo...

Страница 25: ...ows the revision No of the IC 7 6 5 4 3 2 1 0 REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0 1Fh 7 4 SCSI Control Commands 7 4 1 Control Commands and Command Codes Code Command names Summary of commands 00h Reserved 01h Abort_SCSI SCSI Abort command 02h Reserved 03h 04h Assert_RST SCSI Bus Clear command 05h Busfree 06h Reserved 07h Assert_ATN 08h SEL_MSG_clear SCAM control commands 09h Select_WithoutATN ...

Страница 26: ...n the busfree condition though no error occurs It causes no interruption after its execution Any other command under execution continues execution Negation of ATN occurs in any of the following cases When the last byte is ACK negated after Message_Out command was issued If busfree was detected If Assert_RST command was executed If chip reset was done SEL_MSG_clear 08H Negates SCSI SEL MSG signal X...

Страница 27: ...ommand error if issued when any other command is under execution CPU issues this command after setting the command byte number in NON_DMA data size register The command data is written in FIFO The IC acts as follows Waits for busfree Enters arbitration after detecting busfree If it wins arbitration it asserts XSSEL and ID bit entering the selection phase After selection it checks the command phase...

Страница 28: ...nected If issued in the connected condition it sets SCSIINT2 and CMDER bits causing interruption If any other command is under execution then it continues execution If this command is issued set STATN bit5 of SCSIMODE register and clear it when the command is over After the command was issued the IC acts as follows Waits for the SCAM normal selection phase Does not respond to but ignores SCSI sele...

Страница 29: ...t and SCSI usually Setting FIFO bit DMACTL register bit 1 causes the transfer between CPU and SCSI Valid only in the connected condition It can be issued in either Target or Initiator mode If issued in the disconnected condition it sets SCSIINT2 and CMDER bits causing interruption In Target mode Combination of this command issued and the AND condition of DTGO bit of DMACTL register starts DMA tran...

Страница 30: ...in FIFO after the number of bytes to be transferred was set Non DMA_Data_Out can be implemented by setting FIFObit to DMA_Data_Out mentioned above Non DMA_Data_Out can be used only for asynchronous transfer Se we recommend that the operations mentioned above be implemented with the combination of DMA_Data_Out and FIFObit DMA_Data_In 15H Executes SCSI data in phase Transfers data between port and S...

Страница 31: ...ta in phase at the timing of assertion of XSREQ Suspends REQ ACK hand shake until FIFO has some space if FIFO was full If any other phase is found when the data in phase is checked the IC sets ILPHS of SCSIINT1 causing interruption Non DMA_Data_In can be implemented by setting FIFObit to DMA_Data_In mentioned above Non DMA_Data_In can be used only for asynchronous transfer Se we recommend that the...

Страница 32: ...ed after the second byte by checking the message code received Message_Out 19H Executes the message out phase Valid only in the connected condition It can be issued in either Target or Initiator mode If issued in the disconnected condition it sets SCSIINT2 and CMDER bits causing interruption In Target mode CPU sets the byte size of message to be received in NON DMA data size register before issuin...

Страница 33: ...ter It causes interruption Note The message length is fixed at one byte 7 4 3 Command Execution and State Transition The IC has the following three state transitions from the viewpoint of execution of SCSI type commands Disconnected condition D Connected condition in Initiator mode I Connected condition in Target mode T The state transition among those conditions are caused by specific commands as...

Страница 34: ...nterrupt occurs too The firm is asked to check that SCSI 1 selection has occurred by observing SEL interrupt at the same timing when IDERR interrupt occurs Also issue message_out command_out manually while observing the condition of WOATN interrupt because IDERR terminates Wait_selection command Parity error in SCSI data phase or command stop operation by detection of ATN Take note of the followin...

Страница 35: ... Typ Max Unit Supply voltage HVDD 4 50 5 00 5 50 V LVDD 3 00 3 30 3 60 Input voltage HVIN VSS HVDD V LVIN VSS LVDD V Operating temperature Topr 0 25 70 C Input signal rise time Normal input tri 50 ns Input signal fall time Normal input tfi 50 ns Input signal rise time Schmitt input tri 5 ms Input signal fall time Schmitt input tfi 5 ms 8 3 DC Characteristics 1 I O characteristics in the DC conditi...

Страница 36: ... VSS 0V Names of signals covered XSREQ XSACK XCS XRD XWR XPRD XPWR XPDACK PDREQ XRESET TESTEN XSDB0 to 7 XSDBP Item Symbol Conditions Min Typ Max Unit HIGH level trigger Input voltage VT2 HVDD 5 0V 1 2 2 4 V LOW level trigger Input voltage VT2 HVDD 5 0V 0 6 1 8 V Hysteresis voltage VH HVDD 5 0V 0 1 V 5 Pull up down input characteristics Ta 0 to 70 C VSS 0V Names of signals covered AD0 to 4 DB0 to ...

Страница 37: ...ions Min Typ Max Unit 3 state Leak current IOZ HVDD Max 1 1 µA LOW level Output voltage VOL5 HVDD Min IOL 48mA 0 4 V 10 Output characteristics Ta 0 to 70 C VSS 0V IOL 48mA Names of signals covered XSDB0 to 7 XSDBP XSREQ XSACK Item Symbol Conditions Min Typ Max Unit HIGH level Output voltage VOH HVDD Min IOH 20mA 1 5 V 1 LOW level Output voltage VOL HVDD Min IOL 48mA 0 4 V 1 VOH of the active negat...

Страница 38: ...ics Ta 0 to 70 HVDD 5V 10 LVDD 3 3V 0 3V VSS 0V DC level to decide input 0 8V to 2 4V Operating clock foscin 40MHz Loading conditions of output pins except SCSI pins Drives load capacitance of 50pF and 1TTL Load capacitance of SCSI pins Load capacitance 100pF pull up resistance 110Ω pull down resistance 165Ω ...

Страница 39: ...n Min Typ Max Unit T101 XCS fall XRD fall AD 4 0 valid XRD fall 0 ns T102 XRD rise AD 4 0 invalid XRD rise XCS rise 0 ns T103 XRD LOW level pulse width 60 ns T104 XRD HIGH level pulse width 45 ns T105 XRD fall DB 7 0 output 60 ns T106 XRD rise DB 7 0 hold 2 ns XCS AD 4 0 T105 DB 7 0 XRD T101 T103 T102 T106 T104 ...

Страница 40: ... Max Unit T111 XCS fall XWR fall AD 4 0 valid XWR fall 0 ns T112 XWR rise AD 4 0 invalid XWR rise XCS rise 0 ns T113 XWR LOW level pulse width 40 ns T114 XWR HIGH level pulse width 45 ns T115 DB 7 0 valid XWR rise 10 ns T116 XWR rise DB 7 0 hold 0 ns XCS AD 4 0 DB 7 0 XWR T111 T113 T114 T115 T116 T112 ...

Страница 41: ...ecification Min Typ Max Unit T201 XSBSY IN XSBSY OUT OWNID valid 1600 ns T202 XSBSY OUT XSSEL 3000 ns T203 XSSEL SELID valid 1500 ns T204 SELID valid XSBSY OUT 150 ns T205 XSBSY OUT XSBSY IN 500 ns T206 XSBSY IN XSSEL 250 ns XSBSY IN XSSEL XSBSY OUT XSDB0 7 P XSATN XSIO T201 T202 T203 T204 T205 T206 ...

Страница 42: ...t T207 XSBSY IN XSBSY OUT OWNID valid 1600 ns T208 XSBSY OUT XSSEL 3000 ns T209 XSSEL SELID valid XSIO 1500 ns T210 SELID valid XSBSY OUT 150 ns T211 XSBSY OUT XSBSY IN 500 ns T212 XSBSY IN XSBSY OUT 100 ns T213 XSBSY OUT XSSEL 150 ns XSBSY IN XSSEL XSBSY OUT XSDB0 7 P XSIO T207 T209 T208 T210 T213 T212 T211 ...

Страница 43: ... 38 EPSON Rev 1 1 8 4 2 3 Timing of Being Selected Symbol Specification Min Typ Max Unit T214 SELID valid XSBSY IN 0 ns T215 XSBSY IN XSBSY OUT 800 ns T216 XSBSY OUT XSSEL 0 ns XSBSY IN XSSEL XSBSY OUT XSDB0 7 P T215 T216 T214 ...

Страница 44: ... 4 2 4 Timing of Being Selected Symbol Specification Min Typ Max Unit T217 SELID valid XSBSY IN 0 ns T218 XSBSY IN XSBSY OUT 800 ns T219 XSBSY OUT XSSEL 0 ns T220 XSSEL XSBSY OUT 200 ns XSBSY IN XSSEL XSBSY OUT XSDB0 7 P XSIO T218 T217 T219 T220 ...

Страница 45: ...echnical Manual 40 EPSON Rev 1 1 8 4 2 5 XSATN Output Timing Symbol Specification Min Typ Max Unit T221 XSREQ XSATN 25 ns T222 XSATN XSACK 150 ns XSATN XSREQ XSACK XSDB0 7 P XSMSG XSIO XSCD T221 T222 LAST MESSAGE ...

Страница 46: ... 4 2 6 Initiator Asynchronous Data out Timing Data output Symbol Specification Min Typ Max Unit T223 XSREQ XSACK 25 ns T224 XSDB valid XSACK 100 ns T225 XSREQ XSACK 25 90 ns T226 XSACK XSDB invalid 50 ns XSDB0 7 P XSACK XSREQ T224 T223 T225 T226 ...

Страница 47: ... 8 4 2 7 Initiator Asynchronous Data in Timing Data input Symbol Specification Min Typ Max Unit T227 XSDB valid XSREQ 30 ns T228 XSREQ XSACK 25 ns T229 XSACK XSDB invalid 0 ns T230 XSREQ XSACK 25 90 ns XSDB0 7 P XSACK XSREQ T227 T228 T229 T230 ...

Страница 48: ...tput Symbol Specification Min Typ Max Unit T231 XSDB valid XSACK 25 ns T232 XSACK XSDB invalid 25 ns T233 XSACK XSACK 25 ns T234 XSACK NEXT XSACK 25 ns Note Value of when RATE3 to 0bit is 0000 The timing of switching data is the same as in the case of XSREQ rise XSDB0 7 P XSACK T231 T232 T233 T234 ...

Страница 49: ... 8 4 2 9 Initiator Synchronous Data in Timing Data input Symbol Specification Min Typ Max Unit T235 XSDB0 7 P valid XSREQ 6 5 ns T236 XSREQ XSDB0 7 P invalid 5 ns T237 XSREQ XSREQ 11 ns T238 XSREQ XSREQ 11 ns XSDB0 7 P XSREQ T235 T236 T237 T238 ...

Страница 50: ...ynchronous Data in Timing Data output Symbol Specification Min Typ Max Unit T239 XSDB valid XSREQ 100 ns T240 XSACK XSREQ 25 90 ns T241 XSREQ XSDB invalid 50 ns T242a XSACK NEXT XSREQ 25 ns T242b XSREQ XSREQ 150 ns XSDB0 7 P XSREQ XSACK T239 T241 T242b T242a T240 ...

Страница 51: ... Asynchronous Data out Timing Data input Symbol Specification Min Typ Max Unit T243 XSDB valid XSACK 30 ns T244 XSACK XSREQ 25 90 ns T245 XSREQ XSDB invalid 0 ns T246a XSACK XSREQ 25 ns T246b XSREQ XSREQ 150 ns XSDB0 7 P XSREQ XSACK T243 T245 T244 T246a T246b ...

Страница 52: ...utput Symbol Specification Min Typ Max Unit T247 XSDB valid XSREQ 25 ns T248 XSREQ XSDB invalid 25 ns T249 XSREQ XSREQ 25 ns T250 XSREQ XSREQ 25 ns Note Value of when RATE3 to 0bit is 0000 The timing of switching data is the same as in the case of XSREQ rise XSDB0 7 P XSREQ T247 T248 T249 T250 ...

Страница 53: ...v 1 1 8 4 2 13 Target Synchronous Data out Timing Data input Symbol Specification Min Typ Max Unit T251 XSDB valid XSACK 6 5 ns T252 XSACK XSDB invalid 5 ns T253 XSACK XSACK 11 ns T254 XSACK XSACK 11 ns XSDB0 7 P XSACK T251 T252 T253 T254 ...

Страница 54: ...idth 30 ns T306 XPRD XPRD XPRD negate pulse width 30 ns T307 XPRD XPDACK XPRD hold time 0 ns T308 XPRD PD Data output delay time Note 1 0 25 20 Note 2 ns T309 XPRD PD Hi Z Data bus negate time Note 1 6 40 ns Note 1 Data is output to PD only while both XPDACK and XPRD are asserted PD is always in Input mode except such time Note 2 The value in is guaranteed by limiting load capacitance 15pF and 1TT...

Страница 55: ...4 XPDACK XPWR XPWR setup time 0 ns T315 XPWR XPWR XPWR assert pulse width 30 ns T316 XPWR XPWR XPWR negate pulse width 30 ns T317 XPWR XPDACK XPWR hold time 0 ns T318 PD XPWR Data input delay time 10 ns T319 XPWR PD Data hold time 0 ns Note 1 The value in is guaranteed by limiting load capacitance 15pF and 1TTL to driving PDREQ 0 PRQLV 1 XPDACK I XPWR I PD15 0 I XPRD I Direction of data transfer P...

Страница 56: ... XPWR XPWR negate pulse width NP 2 25 ns T337 XPWR XPDACK XPWR hold time 0 5 ns T338 XPWR PD Data output delay time Note 1 0 25 ns T339 XPWR PD Hi Z Data bus negate time Note 1 5 40 ns T33A PDREQ negate XPDACK XPDACK setup time 5 ns Note 1 Data is output to PD only while both XPDACK and XPWR are asserted PD is always in Input mode except such time Direction of data transfer Prosessor S1R72104 HOST...

Страница 57: ...up time 0 5 ns T345 XPRD XPRD XPRD assert pulse width AP 2 25 ns T346 XPRD XPRD XPRD negate pulse width NP 2 25 ns T347 XPRD XPDACK XPRD hold time 0 5 ns T348 PD XPRD Data input delay time 10 ns T349 XPRD PD Data hold time 0 ns T34A PDREQ negate XPDACK XPDACK setup time 5 ns Direction of data transfer Prosessor S1R72104 HOST PDREQ I XPDACK 0 XPRD 0 PD15 0 I T344 T345 T346 T343 T34A T347 T348 T349 ...

Страница 58: ...bol Specification Min Typ Max Unit T400 CLK cycle 1 25 1 f ns T401 CLK HIGH width 1 10 1 f 0 4 15 1 f 0 6 ns T402 CLK LOW width 1 10 1 f 0 4 15 1 f 0 6 ns T403 CLK rise time 5 ns T404 CLK fall time 5 ns 1 T401 402 T400 1 Specified in the same rate also in any cases other than CLK input 40MHz T400 T401 T403 T404 T402 1 9V 0 9V ...

Страница 59: ...cification Min Typ Max Unit T410 CLK cycle 1 25 1 f ns T411 CLK HIGH width 1 10 1 f 0 4 15 1 f 0 6 ns T412 CLK LOW width 1 10 1 f 0 4 15 1 f 0 6 ns T413 CLK rise time 5 ns T414 CLK fall time 5 ns 1 T411 412 T410 1 Specified in the same rate also in any cases other than EXCLK input 40MHz T410 T411 T413 T414 T412 1 9V 0 9V ...

Страница 60: ...Pulse When PLL is operated When PLL is not used the waveform inputted is output to CLKINorEXCLK pin HIGH level is LVDD Symbol Specification Min Typ Max Unit T430 TESTMON cycle 1 25 ns T431 TESTMON HIGH width T431 T430 45 55 ns 1 The accuracy of the output clock depends on the accuracy of the clock oscillated by CLKIN or that inputted to CLKIN EXCLK T420 XRESET T431 T430 TESTMON ...

Страница 61: ...type PD 15 0 PD 15 0 PDREQ PDREQ XPDACK XPDACK XPWR XPWR XPRD XPRD PORT Interface 5V type EXCLK XPLLPD 3 3V PLLCT1 PLLCT0 CLKSEL1 CLKSEL0 VC 100pF OSCIN 5pF OSCOUT 5pF TESTMON open 6 8kΩ 1MΩ 20 0MHz SCSI Interface active terminator DB 7 0 XSDB 7 0 DBP XSDBP ATN XSATN BSY XSBSY ACK XSACK RST XSRST MSG XSMSG SEL XSSEL C D XSCD REQ XSREQ I O XSIO XRESET XRESET HVDD 5V LVDD 3 3V VSS GND TESTEN ...

Страница 62: ...ical Manual Rev 1 1 EPSON 57 10 EXTERNAL DIMENSIONS DRAWING Plastic QFP15 100 pin INDEX 14 0 1 51 75 76 50 16 0 4 14 0 1 26 100 1 25 0 18 0 05 1 7Max 0 1 1 4 0 1 1 0 125 0 025 0 5 0 2 10 0 0 1 0 5 0 05 Unit mm 16 0 4 ...

Страница 63: ... 544 2490 FAX 34 93 544 2491 Scotland Design Center Integration House The Alba Campus Livingston West Lothian EH54 7EG SCOTLAND Phone 44 1506 605040 FAX 44 1506 605041 ASIA EPSON CHINA CO LTD 23F Beijing Silver Tower 2 North RD DongSanHuan ChaoYang District Beijing CHINA Phone 64106655 FAX 64107319 SHANGHAI BRANCH 7F High Tech Bldg 900 Yishan Road Shanghai 200233 CHINA Phone 86 21 5423 5577 FAX 86...

Страница 64: ...In pursuit of Saving Technology Epson electronic devices Our lineup of semiconductors displays and quartz devices assists in creating the products of our customers dreams Epson IS energy savings ...

Страница 65: ...First issue October 2002 Printed in Japan H A EPSON Electronic Devices Website ELECTRONIC DEVICES MARKETING DIVISION SEIKO EPSON CORPORATION http www epsondevice com S1R72104 Technical Manual ...

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