S5U13709 Evaluation Board User Manual
The 12-position DIP switch (SW1) is used to configure the S1D13709 for different host bus
interfaces and for TFT panel or STN panel for TFT-LCD Automatic Setting Mode.
Table 3-1a: Summary of Configuration Options
S5U13709P00C100
SW1-[12:1]
Configuration
S1D13709
Pin
Configuration State
1 (ON)
0 (OFF)
SW1-[12]
TESTEN Not
use
Normal use “GND”
SW1-[11]
CNF10
CLKI (XCG1) frequency is 24MHz
This setting is available only when the TFT-LCD Automatic
Setting Mode is enabled (CNF[7:5] = 001,010, 011 or 100)
CLKI (XCG1) frequency is 20MHz
SW1-[10]
CNF9
TFT Interface Output Drive is [email protected]
(8mA@5V)
This setting is available only when the TFT-LCD Automatic
Setting Mode is enabled (CNF[7:5] = 001,010, 011 or 100)
TFT Interface Output Drive is [email protected]
(3mA@5V)
SW1-[9]
CNF8
All output video signals change at rising edge
of FPSHIFT
This setting is available only when the TFT-LCD Automatic
Setting Mode is enabled (CNF[7:5] = 001,010, 011 or 100)
All output video signals change at the
falling edge of FPSHIFT
SW1-[8:6]
CNF[7:5]
CNF7 CNF6 CNF5 TFT-LCD Automatic Setting Mode
0 0 0 Disable (Manual setting)
0 0 1 S1D13700 S/W: QVGA
→
TFT: QVGA
0 1 0 S1D13700 S/W: QVGA
→
TFT: WQVGA
0 1 1 S1D13700 S/W: QVGA
→
TFT: VGA
1 0 0 S1D13700 S/W: QVGA
→
TFT: WVGA
1 0 1 Reserved
1 1 0 Reserved
1 1 1 Reserved
When the STN interface is used (REG[34h] bit0 = 0), CNF[7:5]
should be 000.
TFT interface is used. (TFT-LCD Automatic
Setting Mode Disable)
Or STN interface is used. (REG[34h] bit0
= 0)
SW1-[5]
CNF4
Indirect Addressing Mode:
1-bit address bus, 8-bit data bus
9pin are used
Direct Addressing Mode:
16bit address bus, 8-bit data bus
24pin are used.
SW1-[4:3]
CNF[3:2]
Select the host bus interface as follows:
CNF3 CNF2 Host Bus
0 0 Generic Bus
0 1 Reserved
1 0 M6800 Family Bus Interface
1 1 MC68K Family Bus Interface
Select the host bus interface as “Generic
Bus”.
SW1-[2:1]
CNF[1:0]
Select the XSCL cycle time (XSCL:CLOCK
Input) as follows:
For 1bpp mode (REG[20h] bit 1-0 = 00)
CNF1 CNF0 XSCL Cycle Time
0 0 4:1
0 1 8:1
1 0 16:1
1 1 Reserved
For 2bpp mode (REG[20h] bit 1-0 = 01)
CNF1 CNF0 XSCL Cycle Time
0 0 8:1
0 1 16:1
1 0 32:1
1 1 Reserved
For 4bpp mode (REG[20h] bit 1-0 = 10)
CNF1 CNF0 XSCL Cycle Time
0 0 16:1
0 1 32:1
1 0 64:1
1 1 Reserved
When the TFT Interface is used (REG[34h] bit0 = 1), CNF[1:0]
should be 00.
For 1bpp mode (REG[20h] bit 1-0 = 00)
CNF1 CNF0 XSCL Cycle Time
0 0 4:1
For 2bpp mode (REG[20h] bit 1-0 = 01)
CNF1 CNF0 XSCL Cycle Time
0 0 8:1
For 4bpp mode (REG[20h] bit 1-0 = 10)
CNF1 CNF0 XSCL Cycle Time
0 0 16:1
= default setting
7 EPSON S5U13709P00C100 Evaluation Board User Manual Rev. 1.00
