S1C88650 TECHNICAL MANUAL
EPSON
35
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (System Controller and Bus Control)
_____ _____
Table 5.2.2.1 Address settings of CE0–CE2
CE0
CE1
CE2
300000H–3FFFFFH
100000H–1FFFFFH
200000H–2FFFFFH
000000H–00D7FFH, 010000H–0FFFFFH
100000H–1FFFFFH
200000H–2FFFFFH
Address range (expansion mode)
CE signal
MCU mode
MPU mode
_____
The output terminals and output circuits for CE0–
_____
CE2 are shared with output ports R30–R32. At
initial reset, they are set as output port terminals.
For this reason, when operating in expansion mode,
_____
the ports to be used as CE signal output terminals
must be set as such.
This setting is performed through software which
writes "1" to registers CE0–CE2 corresponding the
____
CE signals to be used.
Table 5.2.2.1 shows the address range assigned to
____
the three chip enable (CE) signals.
The arrangement of memory space for external
devices does not necessarily have to be continuous
from a subordinate address and any of the chip
enable signals can be used to assign areas in
memory. However, in the MPU mode, program
_____
memory must be assigned to CE0.
____
The CE signals are only output when the appointed
external memory area is accessed and are not
output when internal memory is accessed.
5.2.3 WAIT state settings
In order to insure accessing of external low speed
devices during high speed operations, the S1C88650
is equipped with a WAIT function which prolongs
access time.
The number of wait states inserted can be selected
from a choice of eight as shown in Table 5.2.3.1 by
means of registers WT0–WT2.
Table 5.2.3.1 Setting the number of WAIT states
WT2
Number of inserted states
1
1
1
1
0
0
0
0
14
12
10
8
6
4
2
No wait
WT1
1
1
0
0
1
1
0
0
WT0
1
0
1
0
1
0
1
0
*
The length of one state is a 1/2 clock cycle.
WAIT states set in software are inserted between
bus cycle states T3–T4.
Note, however, that WAIT states cannot be inserted
when an internal register and internal memory are
being accessed and when operating with the OSC1
oscillation circuit (see "5.4 Oscillation Circuits").
Consequently, WAIT state settings in single chip
mode are meaningless.
With regard to WAIT insertion timing, see Section
3.6.5, "WAIT control".
5.2.4 Setting the bus authority release
request signal
With systems performing DMA transfer, the bus
________
authority release request signal (BREQ) input
________
terminal and acknowledge signal (BACK) output
terminal have to be set.
________
The BREQ input terminal is shared with input port
________
terminal K03 and the BACK output terminal with
output port terminal R33. At initial reset, these
terminal facilities are set as input port terminal and
output port terminal, respectively. The terminals
________
________
can be altered to function as BREQ/BACK termi-
nals by writing a "1" to register EBR.
For details on bus authority release, see "3.6.6 Bus
authority release state" and "S1C88 Core CPU
Manual".
5.2.5 Stack page setting
Although the stack area used to evacuate registers
during subroutine calls can be arbitrarily moved to
any area in data RAM using the stack pointer SP, its
page address is set in registers SPP0–SPP7 in I/O
memory.
At initial reset, SPP0–SPP7 are set to "00H" (page 0).
Since the internal RAM is arranged on page 0
(00D800H–00F7FFH), the stack area in single chip
mode is inevitably located in page 0.
In order to place the stack area at the final address
in internal RAM, the stack pointer SP is placed at an
initial setting of "F800H". (SP is pre-decremented.)
In the expansion mode, to place the stack in
external expanded RAM, set a corresponding page
to SPP0–SPP7. The page addresses to which SPP0–
SPP7 can be set are 00H–27H and must be within a
RAM area.
*
A page is each recurrent 64K division of data
memory beginning at address zero.
