Epson S1C63666, Техническое руководство

Страница: 99 / 171

S1C63666 TECHNICAL MANUAL
EPSON
89
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)
4.11.10 Programming notes
(1) When reading counter data, be sure to read the low-order 4 bits (PTDx0–PTDx3) first. Furthermore,
the high-order 4 bits (PTDx4–PTDx7) should be read within 0.73 msec (when f
OSC1
is 32.768 kHz) of
reading the low-order 4 bits (PTDx0–PTDx3).
(2) The programmable timer actually enters RUN/STOP status in synchronization with the falling edge
of the input clock after writing to the PTRUNx register. Consequently, when "0" is written to the
PTRUNx register, the timer enters STOP status at the point where the counter is decremented (-1). The
PTRUNx register maintains "1" for reading until the timer actually stops.
Figure 4.11.10.1 shows the timing chart for the RUN/STOP control.
PTRUNx (WR)
PTDx0–PTDx7 42H 41H 40H 3FH 3EH 3DH
PTRUNx (RD)
Input clock
"1" (RUN)
writing "0" (STOP)
writing
Fig. 4.11.10.1 Timing chart for RUN/STOP control
It is the same even in the event counter mode. Therefore, be aware that the counter does not enter
RUN/STOP status if a clock is not input after setting the RUN/STOP control register (PTRUN0).
(3) Since the TOUT signal is generated asynchronously from the PTOUT register, a hazard within 1/2
cycle is generated when the signal is turned on and off by setting the register.
(4) When the OSC3 oscillation clock is selected for the clock source, it is necessary to turn the OSC3
oscillation ON, prior to using the programmable timer. However the OSC3 oscillation circuit requires
a time at least 5 msec from turning the circuit ON until the oscillation stabilizes. Therefore, allow an
adequate interval from turning the OSC3 oscillation circuit ON to starting the programmable timer.
Refer to Section 4.4, "Oscillation Circuit", for the control and notes of the OSC3 oscillation circuit.
At initial reset, the OSC3 oscillation circuit is set in the off state.
(5) After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag =
"1") is set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure
to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the
interrupt enabled state.
(6) For the reason below, pay attention to the reload data write timing when changing the interval of the
programmable timer interrupts while the programmable timer is running.
The programmable timer counts down at the falling edge of the input clock and at the same time it
generates an interrupt if the counter underflows. Then it starts loading the reload data to the counter
and the counter data is determined at the next rising edge of the input clock (period shown in as
➀
in
the figure).
Input clock
Counter data
(continuous mode)
(Reload data = 25H)
03H 02H 01H 00H 25H 24H
Counter data is determined by reloading. Underflow (interrupt is generated)
➀
Fig. 4.11.10.2 Reload timing for programmable timer
To avoid improper reloading, do not rewrite the reload data after an interrupt occurs until the counter
data is determined including the reloading period
➀
. Be especially careful when using the OSC1 (low-
speed clock) as the clock source of the programmable timer and the CPU is operating with the OSC3
(high-speed clock).