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ETM50E Revision History 

Rev No. 

Date 

Page 

Description 

ETM50E-01 

-- 

 

-- 

ETM50E-02 

05.Oct.2015 

 

Release 

ETM50E-03 

10.May.2016 

1 

Corrected a the block diagram. 

4 

Add description to [3.2. Pin Functions]. 

9 

Corrected  a  [10.1.  Characteristic  for  the  fluctuation  of  the  power 
supply ] 

13 

Corrected a [7) Clock output function] 

27 

Corrected  a  [14.7.2.  Related  register  of  Battery  backup 
switchover function] 

ETM50E-04 

20.Sep.2016 

3 

Updated the Recommended soldering pattern

 

 

Optimization of the text. 

ETM50E-05 

23.Jan.2018 

2 

Added terminal processing when output terminal is not used. 

3 

Added typical value of external dimensions. 

3 

Added recommended soldering pattern.

 

6 

Corrected Max. value of Hihgh- Level input voltage.

 

8 

Corrected reset delay time (at recovery form backup). 

9 

Corrected access wait time. 

20 

Changed 7) TSTP bit related table.

 

21 

Added timer circuit block diagram 

25 

Added alarm circuit block diagram 

27 

Added time update circuit block diagram 

30 

Corrected table operation stages of voltage detection. 

36 

Added comment to wait time. 

37 

Added comments related to STOP bit    in 3)The setting of the 
  clock and calendar. 

42 

Added address circulation table of auto increment function. 

 

 

 

 

 

Содержание RX8130 CE

Страница 1: ...ETM50E 05 Preliminary Application Manual Real Time Clock Module RX8130 CE ...

Страница 2: ...nd any technical information furnished if any for the development and or manufacture of weapon of mass destruction or for other military purposes You are also requested that you would not make the products available to any third party who may use the products for such prohibited purposes These products are intended for general use in electronic equipment When using them in specific applications th...

Страница 3: ... 05 23 Jan 2018 2 Added terminal processing when output terminal is not used 3 Added typical value of external dimensions 3 Added recommended soldering pattern 6 Corrected Max value of Hihgh Level input voltage 8 Corrected reset delay time at recovery form backup 9 Corrected access wait time 20 Changed 7 TSTP bit related table 21 Added timer circuit block diagram 25 Added alarm circuit block diagr...

Страница 4: ...of Functions and Description of Registers 13 13 1 Overview of Functions 13 13 2 Register table 14 13 3 Description of registers 15 14 How to use 17 14 1 Clock calendar explanation 17 14 2 Fixed cycle Timer Interrupt Function 18 14 3 Alarm Interrupt Function 23 14 4 Time Update Interrupt Function 26 14 5 Frequency stop detection function 28 14 6 FOUT function clock output function 28 14 7 Battery b...

Страница 5: ...demark of NXP Semiconductors 1 Overview This is a real time clock module of the serial interface system that incorporates a 32 768 kHz crystal oscillator The real time clock function incorporates not only a calendar and clock counter for the year month day day of the week hour minute and second but also a time alarm interval timer and time update interruption among other features By the backup bat...

Страница 6: ...en VDD and VIO VOUT Internal voltage output pin Connect smoothing capacitor of 1 0uF VBAT This is a power supply pin for backup battery This is a pin to connect a large capacity capacitor a secondary battery and a primary battery In a backup mode the voltage is supplied inside by this pin GND Connected to a ground Note Connect a bypass capacitor rated at least 0 1μF between power supply pins and G...

Страница 7: ... 0 2 Typ 3 24 CE PKG Rev 04 2 5 0 2 Typ 2 54 1 0Max 0 7 0 3 0 62 0 42 0 2 Min 0 4 0 35 0 7 0 4 0 9 1 1 0 3 0 7 0 4 0 9 1 1 Type 1 for small mounting area Type 2 5 2 Marking Layout RX8130CE 1 Pin Mark Logo Production lot R8130 A123B Type Contents displayed indicate the general markings and display but are not the standards for the fonts sizes and positioning ...

Страница 8: ...ts when VDD becomes less than VDET1 1 6 3 0 5 5 V Clock supply voltage VCLK Backup operation mode VBAT 1 1 3 0 5 5 V Operating temperature T_use No condensation 40 25 85 C Minimum value of Clock supply voltage VCLK is the timekeeping continuation lower limit value that initialized RX8130 in operating supply voltage VDD 8 Frequency Characteristics Unless otherwise specified GND 0 V Ta 40 C to 85 C ...

Страница 9: ...s 2 67 2 75 2 83 V Detector Threshold Voltage2 falling edge of VDD VDET12 2 7V setting Reset output 2 62 2 70 2 78 V Detector Threshold Voltage3 rising edge of VDD VDET2 Switching voltage from VBAT to VDD 1 25 1 35 1 45 V Detector Threshold Voltage3 falling edge of VDD VDET2 Switching voltage from VDD to VBAT 1 20 1 30 1 40 V Detector Threshold Voltage1 rising edge of VBAT VDET31 Charge stop volta...

Страница 10: ...IOUT 0 1mA VBAT 0 02 V High level input voltage VIH1 SCL SDA 0 8 VIO 5 5 V Low level input voltage VIL SCL SDA GND 0 3 0 2 VIO V High level output voltage VOH FOUT IOH 1 mA VIO 0 5 VIO V Low level output voltage VOL1 FOUT IOL 1 mA GND GND 0 5 V VOL2 RST IRQ VIO 5 V IOL 1 mA GND GND 0 25 V VOL3 VIO 3 V IOL 1 mA GND GND 0 4 V VOL4 SDA VIO 2 V IOL 3 mA GND GND 0 4 V ...

Страница 11: ...RT CONDITION S BIT 7 MSB A7 BIT 6 A6 ACK A Protocol tBUF tSU STO STOP CONDITION P START CONDITION S P A tHD STA tSU STA S BIT 0 LSB R W S tSP Warning When accessing this device all communication from transmitting the start condition to transmitting the stop condition after access should be completed within 0 95 seconds If such communication requires 0 95 seconds or longer the I2 C bus interface is...

Страница 12: ...LAYF 250 t_str tDELAY ms Timing chart VDD RST tDELAY VDET11 VDET12 t_str tDELAYF t_str is oscillation startup time Item symbol Min Typ Max unit Reset delay time Recovery from Backup t_int t_DELAY tDELAYB 60 95 ms Timing chart VDD RST tDELAY VDET11 VDET12 t_int tDELAYB VDET2 t_int is an intermittence drive timing of a VDET2 detect circuit Maximum value is 35ms ...

Страница 13: ...he RTC by the software Before shifting to a backup operation please transfer stop condition and finish communication as otherwise data might be lost or a time error of 1sec might occur VDD VCLK GND VDD tR1 tF tR2 VDET11 Backup mode tCL tCD tCU VDET11 or VDET12 VDET11 or VDET12 It depends on register setting before a switching to backup I 2 C IF VDD Access is possible VOUT Access is impossible Acce...

Страница 14: ...ge VDET11 Internal oscillation illustration t_str Oscillation start time internal oscillation wait time Access is enabled Normal operation start Minimum voltage for clock maintenance VCLK Min V During power on initialization or power supply voltage recovery after drop in clock maintenance voltage 30 ms After 30 ms progress Confirm a state by VLF bit At the time of VLF 1 After a t_str wait initial ...

Страница 15: ...y deviation in any temperature 1 C2 Coefficient of secondary temperature 0 035 0 005 10 6 C2 T C Ultimate temperature 25 5 C X C Any temperature 2 To determine overall clock accuracy add the frequency precision and voltage characteristics f f f fo fT fV f f Clock accuracy stable frequency in any temperature and voltage f fo Frequency precision fT Frequency deviation in any temperature fV Frequency...

Страница 16: ...auses increase of a consumption electric current and the behavior that are instability Please fix an unused input terminal to the voltage that is near to VIO or GND 2 Notes on packaging 1 Soldering heat resistance If the temperature within the package exceeds 260 C the characteristics of the crystal oscillator will be degraded and it may be damaged The reflow conditions within our reflow profile i...

Страница 17: ...tion time on the main power supply and the operation time on the backup power supply and can automatically sum them up 4 Alarm interrupt function The alarm interrupt function generates interrupt events for alarm settings such as date day hour and minute settings When an interrupt event occurs the AF bit value is set to 1 and the IRQ pin goes to low level to indicate that an event has occurred 5 Ti...

Страница 18: ...ter 32 bit 4 word x 8 bit Address h Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 30 Digital offset DTE L7 L6 L5 L4 L3 L2 L1 1 After the initial power up from 0 V or in case the VLF bit returns 1 make sure to initialize all registers before using the RTC Be sure to avoid entering incorrect date and time data as clock operations are not guaranteed when the data or time data is incorrect ...

Страница 19: ... bit 2 bit 1 bit 0 30 Digital offset 0 0 0 0 0 0 0 0 13 3 Description of registers 13 3 1 Clock and calender counter 10 h 16 h This is counter registers from a second to a year Please refer to 14 1 Clock calendar explanation for details 13 3 2 RAM registers 20 h 23 h This RAM register is read write accessible for any data in the range from 00 h to FF h 13 3 3 Alarm registers 17 h 19 h The alarm in...

Страница 20: ...is bit is to stop a timekeeping operation In the case of STOP bit 1 1 All the update of timekeeping and the calendar operation stops With it an update interrupt event does not occur at an alarm interrupt and the time 2 The part of the fixed cycle timer interrupt function stops A count stops the source clock setting of the timer in case of 64Hz 1Hz 1min 1h 3 Note 3 The effect of STOP bit to FOUT fu...

Страница 21: ...cremented at the timing when carry is generated from a lower register 14 1 2 Week counter The day of the week is indicated by 7 bits bit 0 to bit 6 The day data values are counted as Day 01h Day 02h Day 04h Day 08h Day 10h Day 20h Day 40h Day 01h Day 02h etc It is incremented when carry is generated from the HOUR register This register does not generate carry to a higher register Since this regist...

Страница 22: ... value for the counter Any count value from 1 0001 h to 65535 FFFFh can be set Be sure to write 0 to the TE bit before writing the preset value When TE 0 read out data of timer counter is default Preset value And when TE 1 read out data of timer counter is just counting value But when access to timer counter data counting value is not held Therefore for example perform twice read access to obtain ...

Страница 23: ...bit to zero does not enable the IRQ low output status to be cleared to Hi z 1 Invalid writing a 1 will be ignored Read 0 1 Fixed cycle timer interrupt events are detected Result is retained until this bit is cleared to zero 5 TIE bit Timer Interrupt Enable This bit is used to control output of interrupt signals from the IRQ pin when a fixed cycle timer interrupt event has occurred TIE Data Descrip...

Страница 24: ...X Setting of TSTP value becomes invalid and the count does not stop even if set it in TSTP 1 1 X X The count stops at the time of the setting of 64Hz 1Hz 1 60Hz 1 3600Hz 0 X X X It doesn t start counting 14 2 3 Fixed cycle timer start timing Counting down of the fixed cycle timer value starts at the rising edge of the SCL ACK output signal that occurs when the TE value is changed from 0 to 1 TSEL0...

Страница 25: ... TSEL1 0 0 1 1 Hz TSEL2 0 TSEL1 0 1 0 1 60 Hz TSEL2 0 TSEL1 0 1 1 1 3600 Hz TSEL2 1 TSEL1 0 0 0 0 1 244 14 s 15 625 ms 1 s 1 min 1 h 410 100 10 ms 6 406 s 410 s 410 min 410 h 3840 0 9375 s 60 000 s 3840 s 3840 min 3840 h 4096 1 0000 s 64 000 s 4096 s 4096 min 4096 h 65535 15 9998 s 1023 984 s 65535 s 65535 min 65535 h 14 2 5 Diagram of fixed cycle timer interrupt function IRQ 16 bit counter TE Sou...

Страница 26: ...te interrupt event occurs the UF bit value becomes 1 3 When the UF bit value is 1 its value is retained until it is cleared to zero 4 When a time update interrupt occurs IRQ pin output is low if UIE 1 If UIE 0 when a timer update interrupt occurs the IRQ pin status remains Hi Z 5 Each time an event occurs IRQ pin output is low only up to the tRTN time which is fixed as min 7 57 ms for time update ...

Страница 27: ...set using this register and the WADA bit In the WEEK alarm Day alarm register Reg 19h the setting selected via the WADA bit determines whether WEEK alarm data or DAY alarm data will be set If WEEK has been selected via the WADA bit multiple days can be set such as Monday Wednesday Friday Saturday When the settings made in the alarm registers and the WADA bit match the current time the AF bit value...

Страница 28: ... When an alarm interrupt event occurs an interrupt signal is generated IRQ status changes from Hi z to low The AIE bit is only output control of the IRQ terminal It is necessary to clear an AF flag to cancel alarm 14 3 2 Examples of alarm settings 1 Example of alarm settings when Week has been specified and WADA bit 0 Week is specified WADA bit 0 Week Alarm HOUR Alarm MIN Alarm bit 7 AE bit 6 S bi...

Страница 29: ...nction AIE bit IRQ output AF bit Event occurs 1 0 Hi z L 1 0 Internal operation Write operation Internal minute carry AF Flag AIE IRQ MIN detection result AF 0 clear MIN AE HOUR AE WEEK DAY AE HOUR detection result WEEK detection result DAY detection result 0 1 WADA ...

Страница 30: ... generation of time update interrupt events USEL Data Description Write 0 Selects second update once per second as the timing for generation of interrupt events 1 Selects minute update once per minute as the timing for generation of interrupt events 2 UF bit Update Flag This flag bit value changes from 0 to 1 when a time update interrupt event occurs UF Data Description Write 0 Clearing this bit t...

Страница 31: ...update interrupt function diagram UIE bit IRQ output UF bit Carry tRTN period period period period 1 0 Hi z L 1 0 Internal operation Write operation Carry Sec F64Hz Update Control Circuit USEL bit UF 0 Clear Carry Min tRTN UF Flag UIE bit IRQ ...

Страница 32: ...SEL1 TSEL0 14 6 2 FOUT function table 2 FSEL1 FSEL0 bit FSEL1 FSEL0 output 0 0 32768 Hz Output 0 1 1024 Hz Output 1 0 1 Hz Output 1 1 OFF don t care At the time of the initial power on 0 is set to FSEL1 FSEL0 Note The effect of STOP bit to FOUT functions When STOP 1 32768Hz and 1024Hz output is possible But 1Hz output is disabled 14 7 Battery backup switchover function 14 7 1 Description of Batter...

Страница 33: ...eing set to 0 afterwards CHGEN bit remains valid and active 1 CHGEN bit is active and I F is stopped upon detection of the voltage drop Floating of a pin is permitted Recommended setting 3 State of MOS Switch A list of states Scenarios SW2 SW1 Description A supply voltage is connected to VBAT earlier than connected to VDD OFF OFF The operation does not start until a supply voltage is applied to VD...

Страница 34: ...ection VDET3 and Low VBAT detection VDET4 which will control SW2 Voltage detection VDET1 VDET2 VDET3 and VDET4 times in different operation stages Power supply operation mode VDD operation Backup battery is charging VDD operation Backup battery is fully charged VDD operation After return from backup VDET1 VDD VDET2 SMPTSEL1 0 SW1 Off time 00b default 2ms 2ms 2ms 01b 16ms 16ms 2ms 10b 128ms 128ms 2...

Страница 35: ...vel defined by BFVSEL bit is reached This flag shows a charge state 7 VBLF bit VBLF Data Description Write 0 Cleared to zero to prepare for the next status detection 1 Invalid writing a 1 will be ignored Read 0 1 Low VBAT has been detected VDET4 14 7 3 Power supply control outline SW1 OFF ON OFF ON OFF SW2 OFF ON OFF ON OFF ON charge OFF ON OFF When power is supplied to only VBAT SW1 and SW2 maint...

Страница 36: ...g I F FOUT Stop of the function 3 3V A function of I F and FOUT stops in sync with the RST output 3 3V VDET11 RST Charge stop VDET12 VDET2 VDD Default I F FOUT functioning I F FOUT Stop of the function Charge enable VDET3 VBAT 1 and VDD VBAT VDET11 or VDET12 Register setting 1 When full charge detection was deactivated VDET3 by register setting VBAT is only charged if VDD VBAT A function of I F an...

Страница 37: ...T1 voltage level In case VDD dropps below this level the RST signal is output and the I F and FOUT output are stopped depending on INIEN bit setting RSVSEL Data Description Write Read 0 VDET11 2 75V default 1 VDET12 2 7V 2 RSF bit This bit holds the result of detecting the reset voltage RSF Data Description Write 0 The RSF is cleared to 0 and waiting for next low voltage detection 1 Invalid writin...

Страница 38: ...ffsets the sub second clocks according to the values set in the digital offset register This correction of the second time register occurs every 10 seconds and the level of correction depends on the offset required When outputting a 32 768kHz signal on FOUT pin this function has no influence since the oscillation frequency of the built in crystal does not change by using this function In case of o...

Страница 39: ...However decimals are discarded 0000100 bin is set Negative offset L 7 1 128 11 57 3 05 124 dec However decimals are discarded 1111100 bin is set 14 10 2 Effect of the digital offset function to other functions Because this function adjusts an internal sub second clock this function affects the a Fixed cycle timer interrupt function and FOUT function 1 FOUT funtion 1Hz setting Once in 10 seconds th...

Страница 40: ...llation stabilized VLF stays 0 When an internal oscillation starts 0 writing of VLF is approved Start Wait Wait time of 30 ms is necessary at least Wait time of 35 ms or more is necessary when returning from backup Whether it is a return from the state of the backup is confirmed VLF 1 YES YES NO VLF 0 clear Wait VLF 0 NO Please set waiting time depending on load of a system optionally It takes abo...

Страница 41: ... In such cases stop the fixed cycle timer function by writing 0 to the TE and TIE bits When initialization is finished be sure to set STOP bit to 0 Reg 1C h Set TE bit to 0 Set FSEL1 0 bit optionally Setting the Update function Set the Update interrupt function Setting of the digital offset Reg 30 h When the digital offset function is not being used write 0 in the DTE bit Reg 1E h Set the Battery ...

Страница 42: ... function Next process Reg 1A h 1B h Set initial value of down counter Start count Set TE bit to 1 to start timer interrupt function When start timers interrupt function please surely set reset implement 2 initial value of down counter in advance Reg 1E h Select and set IRQ output Select a power supply condition of a count 1 Countdown is suspended with TSTP 0 1 and countdown is performed again wit...

Страница 43: ...he Alarm interrupt function Next process Reg 1E h Select and set IRQ1 output in AIE bit Reg 1C h Select week or day in WADA bit Reg 1D h Clear AF bit Alarm setting Set AIE bit to 0 to stop Alarm interrupt function Set alarm data Reg 1E h Reg 17 h 19 h ...

Страница 44: ...nications on the I2 C BUS are terminated The SDA level changes from low to high while SCL is at high level 3 Repeated START condition RESTART condition In some cases the START condition occurs between a previous START condition and the next STOP condition in which case the second START condition is distinguished as a RESTART condition Since the required status is the same as for the START conditio...

Страница 45: ...I 2 C bus device CPU etc RX8130 SDA SCL VIO Master Transmitter Receiver Slave Transmitter Receiver Any device that controls the data transmission and data reception is defined as a Master and any device that is controlled by a master device is defined as a Slave The device transmitting data is defined as a Transmitter and the device receiving data is defined as a receiver In the case of this RTC m...

Страница 46: ...g from RX8130 5 Check for ACK signal from RX8130 6 CPU transfers RESTART condition Sr in which case CPU does not transfer a STOP condition P 7 CPU transfers RX8130 s slave address with the R W bit set to read mode 8 Check for ACK signal from RX8130 from this point on the CPU is the receiver and the RX8130 is the transmitter 9 Data from address specified at 4 above is output by the RX8130 10 CPU tr...

Страница 47: ...hai Branch High Tech Building 900 Yishan Road Shanghai 200233 China Phone 86 21 5423 5577 Fax 86 21 5423 4677 Shenzhen Branch Room 804 805 8F Tower 2 Ali Center No 3331 Keyuan South Rosd Shenzhen Bay Nanshan District Shenzhen 518054 China Phone 86 755 3299 0588 Fax 86 755 3299 0560 Epson Hong Kong Ltd Unit 715 723 7 F Trade Square 681 Cheung Sha Wan Road Kowloon Hong Kong Phone 86 755 2699 3828 Sh...

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