Technical Description
14
Seiko Epson Corporation
S5U13743P00C100 Evaluation Board
Rev. 1.1
4.5 Host Interface
4.5.1 Direct Host Bus Interface Support
All S1D13743 host interface pins are available on connector H1 which allows the
S5U13743P00C100 evaluation board to be connected to a variety of development
platforms. For detailed S1D13743 pin mapping, refer to the
S1D13743 Hardware
Functional Specification
, document number X70A-A-001-xx.
The following figure shows the location of host bus connector H1. H1 is a 0.1x0.1”
34-pin header (17x2).
Figure 4-1: Host Bus Connector Location (H1)
For the pinout of connector H1, see “Schematic Diagrams” on page 21.
H1
