
Hardware Manual: emSTAMP- emSBC-Argon (Rev1)
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5.1.2
Boot Configuration
The STM32MP157 offers different boot modes which are selected by the three CPU pins BOOT[2:0].
The different boot modes which are available on the emSTAMP-Argon are shown in the table
below:
BOOT2 BOOT1
BOOT0
Initial boot mode
0
0
0
UART and USB
0
0
1
QUADSPI NOR-Flash
0
1
0
eMMC on SDMMC2 (only fitted on SBC)
1
0
1
SD-Card on SDMMC1
1
1
0
UART and USB
On the emSTAMP-Argon module the three boot configuration pins BOOT[2:0] are connected to 1k
pull-up resistor. The boot pins BOOT[2..0] are connected to the castellated mounting holes of the
module. The desired boot mode has to be set by appropriate setting of these three boot pins on
the carrier board.
Module Pin
CPU Pin Name
Signal
Direction
(module view )
Termination
3
BOOT0
BOOT0
I
PU 1K
4
BOOT1
BOOT1
I
PU 1K
5
BOOT2
BOOT2
I
PU 1K
Note: The emSBC-Argon provides a DIP-switch to set the different boot modes. Please refer to
chapter 6.11 “Boot configuration DIP-Switch” for details how to set the boot mode on the emSBC-
Argon by the DIP-switch.
5.2
DDR3L SDRAM
The emSTAMP-Argon CPU module provides up to 512MiB DDR3L SDRAM as main memory. The
RAM is connected via a 16 bit width data bus und may be clocked up to 533MHz.
5.3
QSPI-NOR Flash
A 16-Mibit QSPI-NOR flash memory (IS25LP016D form ISSI) is integrated on the CPU module. It is
used to hold the initial Bootloader that provides the basic boot functionality of the module. The
flash is connected to the QUAD-SPI bank1 with Quad-SPI-lines.
Module Pin
CPU Pin Name
Signal
-
PF8
QUADSPI_BK1_IO0
-
PF9
QUADSPI_BK1_IO1
-
PF7
QUADSPI_BK1_IO2
-
PF6
QUADSPI_BK1_IO3
-
PB6
QUADSPI_BK1_CS#
-
PF10
QUADSPI_CLK
Internal connection of QSPI-NOR-flash on the CPU-module