EMC Symmetrix DMX-3, Руководство по эксплуатации продукта

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118 EMC Symmetrix DMX-3 Product Guide
Performance and Optimization
Global memory
ASICs The global memory directors expedite transactions between process
requests and global memory. EMC’s global memory directors use
Application Specific Integrated Circuits (ASICs) technology that acts
as intelligent offload engines to perform repetitive system critical
functions. Global memory ASICs consist of the following
components:
◆
“Parallel global memory regions” on page 118
◆
“Buffering” on page 118
◆
“Access arbitration” on page 118
◆
“Memory striping” on page 118
Parallel global
memory regions
Symmetrix DMX-3 global memory architecture drastically reduces
memory contention by partitioning the global memory into four
separately addressable, simultaneously accessible regions. In a
Symmetrix DMX-3 with eight global memory directors, there are 32
separately addressable and accessible global memory regions. The
DMX-3 with four global memory directors supports 16 separately
addressable and accessible global memory regions.
Buffering Global memory ASICs buffer incoming requests from front-end
channel directors and, as soon as possible, free up the global memory
region being accessed. The result is a truly nonblocking architecture
that is capable of massive performance scaling.
Access arbitration Global memory directors also arbitrate incoming requests for global
memory resources in such a way as to optimally allocate global
memory regions to incoming requests by appropriately timing and
intelligently prefetching required information from global memory
into the buffer. This results in optimal utilization of available
resources.
Memory striping To eliminate any contention that may occur while working with large
chunks of data, global memory directors stripe any data that resides
on global memory across all the four regions within each global
global memory director. Striping is carried out in units of 64 memory
words
1
across the four regions of each global memory director.
1. David E. Culler, Jaswinder Pal Singh, 1999: Parallel Computer Architecture, Morgan Kaufmann.