ming operation was successful. If the verify
returns ‘ok’ the next byte is programmed.
The length of the programming pulse
depends on the programming algorithm
applied. The same goes for repetition of the
programming cycle if the relevant byte was
not successfully programmed.
During normal use of the EPROM (V
pp
and
V
cc
at 5 V), the device will respond ‘nor-
mally’ to signals applied to the CS and OE
pins. Only with both inputs activated (i.e., at
logic Low) will the EPROM supply the data
belonging with the address placed on the
address bus.
Practical Circuit
The circuit diagram shown in
Figure 1
com-
prises relatively few components — three
ICs, a voltage regulator, one FET and two
indicator LEDs do the job. IC2 is not an inte-
grated circuit but an assembly of two 14-way
pinheaders that form the connections of the
EPROM being emulated by the circuit.
IC3, a RAM type 62C256, forms the heart
of the circuit. Although a 70-ns version is
specified in the parts list, a faster chip is, of
course, also allowed. Slower versions, how-
ever, are not recommended for use in this cir-
cuit.
IC4 is a GAL type 16V8 which has been
programmed to supply a fair amount of (invis-
ible) logic circuitry that ‘translates’ external
signals to the ones required by IC3. This
translation process requires the GAL to be
connected to the EPROM socket via a few
logic links, as well as to be provided with
information as to the presence of an external
voltage at the V
cc
pin, and a voltage greater
than 12 V at the V
pp
pin.
The combination R3-D3 affords protection
of the GAL against higher voltages at the
EPROM V
cc
pin. That is necessary because
this voltage is usually raised to +6 V during
programming. The circuit around transistor
T1 detects the programming voltage at the
V
pp
connection of the EPROM socket. Zener
diode D1 starts to conduct if the program-
ming voltage is present. The voltage at the
gate of T1 is then high enough for the FET to
be switched on. In combination with resistor
R1, zener diode D1 lowers the voltage to
about 7.5 V, thus ensuring that the FET
remains securely switched off at a voltage of
5 V at the V
pp
terminal.
IC5, then, acts as a buffer device between the
MICRO
PROCESSOR
14
Elektor Electronics
11/2002
*IDENTIFICATION
024066;
*TYPE
GAL16V8;
*PINS
% Pin-assignment for input signals %
EPVP = 8, % Detection of 5V supply %
/EPVPP = 3, % Low active detection of VPP > 12V %
/EPOE = 1, % Input for /OE from EPROM-socket %
/EPCS = 2, % Input for /CS form EPROM-socket %
/SW1 = 9, % Input for switch S1 %
/SW2 = 11, % Input for switch S2 %
% Pin-assignment for output signals %
/RAMCS.t = 15, % output for /CS of RAM IC3 %
/RAMOE.t = 14, % output for /OE of RAM IC3 %
/RAMWR.t = 13, % output for /WR of RAM IC3 %
/BLANK.t = 16, % BLANK-state output for LED D5 %
/PROGRAM.t = 17, % PROGRAM-detect output for LED D4 %
/BUGATE.t = 19, % output for /G of buffer IC 5 %
BUDIR.t = 18; % output for DIR of buffer IC 5 %
*BOOLEAN-EQUATIONS
RAMCS.e = VCC; % These lines make sure that all used %
RAMOE.e = VCC; % output-lines of the GAL are %
RAMWR.e = VCC; % constantly driven %
BLANK.e = VCC;
PROGRAM.e = VCC;
BUGATE.e = VCC;
BUDIR.e = VCC;
% Switch to BLANK-state is S1 is pressed and hold this state %
% Until the EPROM programmer wishes to program the EPROM %
% OR the user wishes to switch to normal operation by pressing %
% S2 %
% This signal also drives LED D5 to indicate the BLANK-mode %
BLANK = BLANK*/PROGRAM*/SW2+SW1 ;
% Detection of a programming pulse to drive LED D4 %
PROGRAM = EPVPP*EPCS*/EPOE;
% CS for the RAM : Continuous during programming, else equal %
% to CS on the ROM %
% Only active during presence of external power to save the %
% battery %
RAMCS= EPVPP*EPVP+/EPVPP*EPCS*EPVP;
% OE for the RAM : During programming if OE on the ROM is %
% active AND Cs of the ROM is inactive %
RAMOE= EPVPP*EPOE*/EPCS + /EPVPP*EPOE*/BLANK;
% WR for the RAM : During programming if ROM-OE is inactive %
% AND ROM-CS is inactive, else if in BLANK-mode AND ROM-OE %
% is active. This means that reading while in blank-mode %
% causes the RAM to be written. Pull-ups make sure that the %
% code 0xFF will be written %
RAMWR= EPVPP*EPCS*/EPOE + /EPVPP*BLANK*EPOE;
% The DIR-signal for the 74HCT245. When this pin is active, %
% Data is transferred from the socket to the RAM-IC %
% Otherwise, the datapath is FROM the RAM to the socket %
BUDIR = EPVPP*/EPOE;
% The GATE-signal for the 74HCT245. If it is active (low) %
% the drivers are active, otherwise the A and B pins are %
% in High-Z state %
% It has to be active even in the BLANK-mode, so it wil force%
% 0xFF on the external databus during blank-check! %
% BUGATE is only active when external power is supplied to %
% save power from the battery whenever the device is not %
% required to be active %
BUGATE=EPVP*EPVPP*EPOE + EPVP*EPVPP*EPCS + EPVP*/EPVPP*EPOE;
*END
Figure 2. JEDEC file listing of the GAL contents.
Содержание EPROM
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