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Real-Time Clock
U3 is a real-time clock chip, incorporating clock and calendar functions. Y1 establishes the oscillator
frequency of 32.768 kHz, with C6 to act as a fine adjustment.
U1 communicates with U3 over a 4-wire serial bus. This is used to set the time and date, and read them
back.
The clock runs even when the K2 is powered off. Lithium cell BT1 provides a nominal 3V level to operate
U3 via Shottky diode D4. When the K2 is operating, +5V is supplied to the clock via Shottky diode D1.
Under this circumstance, the Lithium cell is idle. Shottky diodes are used to minimize voltage drop.
Capacitor C7 provides decoupling of the power supply to U3.
DSPx
The DSPx schematic is on a separate sheet.
In3.6 to +5.5 VDC is applied to voltage regulators U1 (su3.3V for digital circuitry) and
U8 (su3.3VDC for analog circuitry). U2 pr1.8 VDC for operating the DSP core and the
CODEC core.
Incoming audio is applied to U6, a TLV320AIC23 CODEC (encoder-decoder), which contains a pair of 16-
bit analog-to-digital (ADC) and digital-to-analog (DAC) converters, as well as gain controllable amplifiers
and a pair of serial interfaces.
U5, an Analog Devices® ADSP-218xN series DSP chip, controls the CODEC (via U9, a Xilinx complex
programmable logic device, or CPLD). It also has a serial interface that, with suitable modification through
the CPLD, accepts ADC information and provides data to the DAC.
The program for the DSP is contained in the Flash memory, U3. At boot-up, the DSP fetches its program
from the Flash, and then runs the program from internal memory. The Flash memory also contains
numerous coefficient files for the various filters. These are fetched from the Flash on an as-needed basis.
The DSP is clocked by a 40 MHz oscillator, consisting of resonator RES1 and amplifier U4. This results in
an internal instruction rate of 80 million instructions/second.
At power up, U7 provides a reset signal of sufficient duration to allow the DSP clock systems to operate
and settle.
