PC4-PRESTO • CompactPCI
®
PlusIO • 4
th
Generation Intel
®
Core™-4xxx Processor
LAN Subsystem
The Ethernet LAN subsystem is composed of four Gigabit Ethernet ports: One Intel i217LM Physical
Layer Transceiver (PHY) using the PCH QM87 internal MAC and three Intel i210IT Gigabit Ethernet
Controllers. These devices provide also legacy 10Base-T and 100Base-TX connectivity. Two of the
Ethernet ports are fed to two RJ45 jacks located in the front panel, the others are attached to the
CompactPCI
®
Serial interface on J2. Each port includes the following features:
<
One PCI Express lane per Ethernet port (250MB/s)
<
1000Base-Tx (Gigabit Ethernet), 100Base-TX (Fast Ethernet) and 10Base-T (Classic Ethernet)
capability.
<
Half- or full-duplex operation.
<
IEEE 802.3u, 802.3ab Auto-Negotiation for the fastest available connection.
<
Jumperless configuration (complete software-configurable).
Two bicoloured LEDs integrated into the dedicated RJ-45 connector in the front panel are used to
signal the LAN link, the LAN connection speed and activity status. A further bicoloured LED in front
panel labelled EB displays the state of the backplane network ports.
Each device is connected by a single PCI Express lane to the PCH. Their MAC addresses (unique
hardware number) are stored in dedicated FLASH/EEPROM components. The Intel Ethernet software
and drivers for the i217LM and i210IT are available from Intel's World Wide Web site for download.
When managing the board by Intel Active Management Technology (iAMT), the dedicated network
port to do so is accessible by the RJ45 connector GbE1 (the upper port within the front panel).
Although any of the i210 controllers support the IEEE 1588 Precision Time Protocol, the one
connected to GbE2 (the lower port within the front panel) is capable to generate Pulse per Second
(PPS) and Pulse per Minute (PPM) signals that may be routed to the jumper J-GP and the CompactPCI
®
Serial connector P1. These signals can be used to trigger events on Mezzanine Side Boards or
Peripheral Boards. The following routing is possible by UEFI BIOS settings:
<
Pulse per Second (PPS): J-GP Pin 1 and CompactPCI
®
Pin J3 (signal SATA-SCL)
<
Pulse per Minute (PPM): CompactPCI
®
Pin H3 (signal SATA-SDO)
© EKF -25- ekf.com
