Small Logo (EPA) Show (Disabled)
Enables or disables the display of the EPA logo during boot.
Advanced Chipset Setup
The parameters in this screen are for system designers, service personnel,
and technically competent users only. Do not reset these values unless you
understand the consequences of your changes.
Phoenix – AwardBIOS CMOS Setup Utility
Advanced Chipset Features
Item Help
DRAM Clock/Timing Control
[Press Enter]
AGP & P2P Bridge Control
[Press Enter]
Prefetch
Caching
[Disabled]
System BIOS Cacheable
[Disabled]
Video RAM Cacheable
[Disabled]
Memory Hole at 15M-16M
[Disabled]
Menu Level
↑
↓
→
←
: Move
Enter : Select
+/-/PU/PD:Value:
F10: Save ESC: Exit F1:General Help
F5:Previous Values
F6:Fail-Safe Defaults
F7:Optimized Defaults
DRAM Clock/Timing Control
Scroll to this item and press <Enter> to view the following screen:
Phoenix – AwardBIOS CMOS Setup Utility
DRAM Clock/Timing Control
Item Help
DRAM Timing Control
[By SPD]
x DRAM CAS Latency 2.5T
x RAS Active Time (tRAS) 6T
x RAS Precharge Time (tRP) 3T
x RAS to CAS Delay (tRCD) 3T
DRAM Addr/Cmd Rate
[Auto Mode]
Menu Level
↑
↓
→
←
: Move
Enter : Select
+/-/PU/PD:Value:
F10: Save ESC: Exit F1:General Help
F5:Previous Values
F6:Fail-Safe Defaults
F7:Optimized Defaults
DRAM Timing Control (By SPD)
Enables you to select the CAS latency time in HCLKs of 2, 2.5, or 3. The
value is set at the factory depending on the DRAM installed. Do not change
the values in this field unless you change specifications of the installed DRAM
or the installed CPU.
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