L4IBMG2 / L4IBMGL2 V1.0b
34
Advanced Chipset Features
These items define critical timing parameters of the mainboard. You should
leave the items on this page at their default values unless you are very famil-
iar with the technical specifications of your system hardware. If you change
the values incorrectly, you may introduce fatal errors or recurring instability
into your sys tem.
Phoenix – AwardBIOS CMOS Setup Utility
Advanced Chipset Features
Item Help
DRAM Timing Selectable
[Manual]
CAS Latency Time
[2.5]
Active to Precharge Delay
[7]
DRAM RAS# to CAS# Delay [3]
DRAM RAS# Precharge
[3]
DRAM Data Integrity Mode [Non-ECC]
Memory Frequency For
[Auto]
System BIOS Cacheable
[Disabled]
Video RAM Cacheable
[Disabled]
Memory Hole At 15M-16M
[Disabled]
Delayed Transaction
[Enabled]
On-chip Video Windows Size [128]
On-chip Frame Buffer Size [8M]
AGP Aperture Size (MB)
[128]
Delay Prior to Thermal
[16 Min]
Menu Level
↑
↓
→
←
: Move Enter : Select
+/-/PU/PD:Value: F10: Save ESC: Exit F1:General Help
F5:Previous Values
F6:Fail-Safe Defaults
F7:Optimized Defaults
DRAM Timing Selectable (Manual)
The value in this field depends on performance parameters of the installed
memory chips (DRAM). Do not change the value from the factory setting
unless you install new memory that has a different performance rating than
the original DRAMs.
CAS Latency Time: (2.5)
When synchronous DRAM is installed, the number of clock cycles of CAS
latency depends on the DRAM timing. Do not reset this field from the default
value specified by the system designer.
Active to Precharge Delay (7)
The precharge time is the number of cycles it takes for DRAM to accumulate
its charge before refresh.
DRAM RAS# to CAS# Delay (3)
This field lets you insert a timing delay between the CAS and RAS strobe sig-
nals, used when DRAM is written to, read from, or refreshed. Disabled gives
faster performance; and Enabled gives more stable performance.
DRAM RAS# Precharge (3)
Select the number of CPU clocks allocated for the Row Address Strobe
(RAS#) signal to accumulate its charge before the DRAM is refreshed. If insuf-
ficient time is allowed, refresh may be incomplete and data lost.