
Network Connection
The network connection (NET_A and NET_B) is polarity insensitive, and therefore
either of the two twisted pair wires can be connected to either of the two NET pins.
Details on network wiring are discussed in Chapter 5.
Transient protection may be required to protect the LPT-11 transceiver against
surge voltages resulting from network transients and lightning strikes. Details on
surge protection are discussed in Chapter 6.
Clock Input
The LPT-11 transceiver receives its clock input from the Neuron Chip via the CMOS
input CLK pin. This pin is driven by the CLK2 output of the Neuron Chip, whether
the Neuron Chip's oscillator or an external clock oscillator is used. Clock traces
should be kept short (
≤
2cm) to minimize noise coupling.
The LPT-11 transceiver can operate at 20, 10, 5, or 2.5MHz. Operation at 2.5MHz
does not comply with L
ON
M
ARK
interoperability guidelines for the TP/FT-10 channel.
1.25 MHz operation is not supported. The operating frequency is automatically
detected on the CLK pin.
Neuron Chip Communications Port (CP) Lines
The LPT-11 transceiver transmits and receives LonTalk
®
network packets via the
Neuron Chip's direct, single-ended mode over CP0-1. CP0 is the data input to the
Neuron Chip and is connected to the LPT-11 transceiver's RXD pin. CP1 is the data
output from the Neuron Chip and is connected to the TXD pin. These connections
are summarized in table 2.2.
Table 2.2
Neuron Chip
CP Line Connections
Neuron Chip Pin
Neuron Chip Function
LPT-11 Pin
CP0 Data
input RXD
CP1 Data
output TXD
PC Board Layout Guidelines
The recommended PC board layout for the LPT-11 transceiver and its external
components is shown in figure 2.2.
2-4
Electrical Interface
Содержание LonWorks LPT-11
Страница 20: ...2 10 Electrical Interface ...
Страница 40: ...5 14 Network Cabling and System Performance ...
Страница 70: ...B 4 Appendix B Differences Between LPT 10 and LPT 11 ...
Страница 76: ...C 6 Appendix C Checklist ...