e2v TSEV81102G0FS, Руководство пользователя

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Package Description
5-2 TSEV81102G0FS Evaluation Board User Guide
0974C–BDC–02/09
e2v semiconductors SAS 2009
ADCDelAdjIn 44 In-phase input of the stand-alone delay cell
ADCDelAdjInB 45 Inverted phase input of the stand-alone delay cell
Output Data
A[0…9]B[0…9]C[0…9]
D[0…9]E[0…9]F[0…9]
G[0…9]H[0…9]
179, 180, 182, 183, 185, 186, 187, 188, 190,
191, 56, 57, 59, 60, 62, 63, 65, 66, 67, 68, 165,
166, 168, 169, 170, 171, 173, 174, 175, 176,
71, 72, 74, 75, 76, 77, 79, 80, 81, 82, 150, 151,
153, 154, 156, 157, 158, 159, 161, 162, 85, 86,
88, 89, 90, 91, 93, 94, 96, 97, 131, 132, 134,
135, 137, 138, 139, 140, 142, 143, 104, 105,
107, 108, 110, 111, 113, 114, 116, 117
Output data
RefA to RefH 178, 55, 164, 70, 149, 84, 129, 103
Reference outputs (tied to the common mode voltage of
each port)
DR 125
In phase data ready signal (centered on the output data,
frequency = output data/2)
DRB 124
Inverted phase data ready signal (centered on the
output data, frequency = output data/2)
TTL Input Signals
ClkInType 51
Input clock type:
- DR mode = logic “1”
- DR mode = logic “0”
RatioSel 120
DMUX ratio selection:
- 1:4 mode = logic “0”
NbBit 52
Number of bits selection:
- 10 bits = logic “1”
- 8 bits = logic “0”
AsyncReset 192 Asynchronous reset (active high)
BIST 54 Built-in self-test mode (active low)
Other Output Signals
ADCDelAdjOUT 41 In-phase output of the stand-alone delay cell
ADCDelAdjOUTB 42 Inverted phase output of the stand-alone delay cell
Table 5-1. Pin Description (Continued)
Symbol Pin Number Description