e2v CCD42-90 Скачать руководство пользователя страница 8 | Manualshive

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e2v CCD42-90 Скачать руководство пользователя страница 8

© e2v technologies (uk) limited 2014

Document subject to disclaimer on page 1

A1A-100026 Version 9, page 8

NOTES

8.

All pulse low levels should be within range 0 ± 0.5 V, except read-out register clocks about +1 V higher.

9.

Devices can be operated with the substrate at either low (0V) or higher (9V) values. Low substrate is particularly
recommended for deep-depletion variants, since it maximizes the depletion depth for best Point Spread Function. High
substrate minimises the dark current.

10.

Non-charge-dumping level is shown. For charge dumping DG should be pulsed to within 12 ± 2 V.

11.

OG1 is typically set to 3 V. Then, for operation in the high responsivity, low noise mode 1, OG2 should be set 1 V higher at
typically 4 V. For operation in the low responsivity, increased charge handling mode 2, OG2 should be set to +20 V.

12.

Do not connect to voltage supply but use a 3 - 5 mA current source or a 5 - 10 k

Ω

external load connected to 0 V. The

quiescent voltage on OS is then typically within a range 6 - 8 V above the RD voltage. The maximum current is 10 mA.

13.

U309 data: VGD and VGS absolute maximum = -25V.

14.

These connections are for an optional temperature sensor; consult factory for availability.

PIN CONNECTIONS (View facing underside of package)

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Содержание CCD42-90

Страница 1: ...egister is designed to accommodate four image pixels of charge and a summing well is provided capable of holding that from six image pixels The output amplifier has a feature to enable the responsivit...

Страница 2: ...grade b Maximum register capacity c Output node capacity under different modes 3 For highest responsivity and lowest nose mode 1 the voltage on OG2 should be 1V higher than that on OG1 For increased c...

Страница 3: ...neration rate is 5 e pixel s at 173 K which is also equivalent to 100 e hour at 153 K The temperature dependence is the same as for the mean dark signal see note 6 above Black spots A black spot defec...

Страница 4: ...band Deep depletion silicon Astro Midband Deep depletion silicon Astro ER1 response Deep depletion silicon Astro Multi 2 Maximum Pixel Response Non Uniformity PRNU 1 Wavelength nm Minimum QE Minimum Q...

Страница 5: ...es of charges as they are transferred from the image section At either end of the register are an additional 50 elements leading to the charge detection amplifiers The last clocked electrodes are sepa...

Страница 6: ...st applications the output at OS will be used with external load 1 that can be either a 3 5 mA current source or a 5 10 k resistor RL JD and OP and external load 2 are left unconnected In this mode th...

Страница 7: ...1 3 4 20 B2 DD L Dump drain 22 24 26 0 3 to 30 B7 DD R Dump drain 22 24 26 0 3 to 30 D2 OG2 L Output gate 2L See Note 11 20 D7 OG2 R Output gate 2R See Note 11 20 B1 OD L Output drain L 27 29 32 0 3...

Страница 8: ...wn For charge dumping DG should be pulsed to within 12 2 V 11 OG1 is typically set to 3 V Then for operation in the high responsivity low noise mode 1 OG2 should be set 1 V higher at typically 4 V For...

Страница 9: ...te voltage starts to increase from zero It is also important to ensure that excess currents see Note 12 do not flow in the OS pins Such currents could arise from rapid charging of a signal coupling ca...

Страница 10: ...Document subject to disclaimer on page 1 A1A 100026 Version 9 page 10 FRAME READOUT TIMING DIAGRAM DETAIL OF LINE TRANSFER I 1 I 2 I 3 R 1 R 2 R R 3 toi toi toi toi toi tdtr tdrt I 1 I 2 I 3 R 1 R 2 R...

Страница 11: ...DETAIL OF OUTPUT CLOCKING tWX tdX Reset feed through Signal output Reset sampling window Signal sampling window Trr R 1 R 2 R R 3 Output tWX tdX Reset feed through Signal output Reset sampling window...

Страница 12: ...read out R 1 tdrs tdg2 tdg3 tdg4 tdg1 tdsr Line transfer into register Dump charge into drain Next line read out Line transfer into register DETAIL OF VERTICAL LINE TRANSFER MULTIPLE LINE DUMP 1 2 R...

Страница 13: ...clock cycle period 300 see Note 16 see Note 15 ns trr Register pulse rise time 10 to 90 50 0 1Tr 0 3Tr ns tfr Register pulse fall time 10 to 90 trr 0 1Tr 0 3Tr ns tor Register clock pulse overlap 50 0...

Страница 14: ...gies uk limited 2014 Document subject to disclaimer on page 1 A1A 100026 Version 9 page 14 PACKAGE DETAIL Package Mass 150 g approx Inactive edge spacing Sides 260 50 m Top 120 50 m Bottom bond connec...

Страница 15: ...GY RADIATION Performance parameters will begin to change if the device is subject to ionising radiation Characterisation data is held at e2v technologies with whom it is recommended that contact be ma...

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