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AT84CS001-EB Evaluation Kit User Guide

4-1

 0904C–BDC–09/07

Section 4

Application Information

4.1

Introduction

For this section, please also refer to the "Main features" section in the ”AT84CS001” 
reference 0809.

4.2

Input Data

The input data (I0, I0N…I9, I9N and IOR, IORN) and clock (CLK, CLKN) as well as the 
DAI, DAIN input data of the standalone delay cell are LVDS compatible (on-chip 100

Ω

).

Figure 4-1.  

Input Data and Clock Signals

4.3

Digital Outputs

The digital outputs (data and Data Ready) are LVDS compatible. The 100

Ω

 differential 

termination is provided on-board.

5 0

Ω

  line 

Data or clock  
inverted phase signal  

Data or clock in 
phase signal

5 0

Ω

  line 

Содержание AT84CS001-EB

Страница 1: ...AT84CS001 EB Evaluation Board User Guide...

Страница 2: ......

Страница 3: ...2 6 DMUX Functions 3 2 7 Power Supplies 3 Section 3 Operating Characteristics 1 3 1 Introduction 1 3 2 Operating Procedure 1 3 3 Electrical Characteristics 2 Section 4 Application Information 1 4 1 In...

Страница 4: ...ii AT84CS001 EB Evaluation Board User Guide 0904C BDC 09 07 Ordering Information 1 Section 7 Appendix 1 7 1 AT84CS001 EB Electrical Schematics 1 7 2 AT84CS001 EB Board Layers 5...

Страница 5: ...0 bit 2 2 GHz DMUX device SMA connectors for the standalone delay cell inputs and outputs and for the reset input accesses and 2 54 mm pitch con nectors compatible with high speed acquisition system p...

Страница 6: ...s are 220 mm x 230 mm The board comes fully assembled and tested with the AT84CS001 installed Figure 1 1 Simplified Schematics of the AT84CS001 EB Evaluation Board As shown in Figure 1 1 different pow...

Страница 7: ...of the board s structure Table 2 1 Board Structure Layer Characteristics Layer 1 Copper layer Copper thickness 40 m Input and output signals traces 50 microstrip lines Layer 2 RO4003 dielectric layer...

Страница 8: ...pper row is dedicated to the data and clock signals The lower row is connected to ground Each differential signal pair is separated by a connection to ground as illustrated in Figure 2 1 Figure 2 1 In...

Страница 9: ...outputs are floating must be terminated by 100 termination 2 6 DMUX Functions Two potentiometers are provided for the DMUX input clock delay control CLKDACTRL and the standalone delay cell control DA...

Страница 10: ...User Guide 0904C BDC 09 07 Each power supply is decoupled as close as possible to the AT84CS001 device by 10 nF in parallel with 100 pF surface mount chip capacitors Note The decoupling capacitors are...

Страница 11: ...VCCD 3 3V VPLUSD 2 5V and 3 3V 2 Connect the clock input signals CLK CLKN This clock may be single ended or differential Use a low phase noise high frequency generator You should use an LVDS signal to...

Страница 12: ...miting values referenced to GND 0V to be applied individually while other parameters are within specified operating conditions Long exposure to maximum rating may affect device reliability All integra...

Страница 13: ...age VCCD 3 15 3 3 3 45 V Output power supply voltage VPLUSD 2 375 2 5 2 625 V Digital power supply current 1 2 mode 1 4 mode SLEEP mode Additional current with SDA enabled Additional current with BIST...

Страница 14: ...VCCD 3 V Reset input ASYNCRST Logic compatibility LVCMOS CMOS Control input voltages Logic low Logic high Common mode VIL VIH VICM 0 1 5 1 4 1 2 3 3 V Table 3 3 Electrical Operating Characteristics C...

Страница 15: ...ata to Data Ready propagation delay TD1 0 3 0 333 500 ps Data Ready to output data propagation delay TD2 0 3 0 333 500 ps Output data pipeline delay Synchronized 1 2 mode Synchronized 1 4 mode Stagger...

Страница 16: ...Operating Characteristics 3 6 AT84CS001 EB Evaluation Kit User Guide 0904C BDC 09 07...

Страница 17: ...ta The input data I0 I0N I9 I9N and IOR IORN and clock CLK CLKN as well as the DAI DAIN input data of the standalone delay cell are LVDS compatible on chip 100 Figure 4 1 Input Data and Clock Signals...

Страница 18: ...gnal in inactive mode Figure 4 3 ASYNCRST Function If the DRRB reset is also used we recommend to apply the asynchronous reset while the DRRB reset is active The first data is available at the device...

Страница 19: ...CTRL Function 4 4 3 DACTRL A standalone delay cell is available input DAI DAIN output DAO DAON control DACTRL enable DAEN This cell allows you to delay the incoming signal DAI DAIN by approximately 25...

Страница 20: ...ut Inactive normal mode BIST jumper ON No BIST jumper OUT CLKTYPE Input clock mode CLK data valid on each rising edge of the CLK CLKN signal CLK 2 data valid on both rising and falling edges of the CL...

Страница 21: ...ormation AT84CS001 EB Evaluation Kit User Guide 4 5 0904C BDC 09 07 Figure 4 5 Jumper Positions of DMUX Functions Jumper ON Jumper OUT BIST BIST STAGG SLEEP CLKTYPE DAEN RS DRTYPE STAGG SLEEP CLKTYPE...

Страница 22: ...4CS001 DEMUX AT84AS008 Power supplies GW PPT 0o C Balun MACOM H9 Acquisition board Power supplies GW PPT HP16500C analysis logic A B C D GPIB bus LabView Fs ADC sampling data Clock HP86665B sinewave s...

Страница 23: ...D VCCD VCCD VCCD VCCD VCCD VCCD VCCD VCCD DGND CLKTYPE DACTRL DAEN BIST VCCD D9N D9 VPLUSD VPLUSD D8 D8N D7N D7 VPLUSD VPLUSD VCCD D6 D6N D5N D5 VPLUSD VPLUSD D4 D4N D3N D3 VPLUSD VPLUSD D2 D2N D1N D1...

Страница 24: ...8 N18 P18 Inverted phase digital input signal IORN B18 In phase digital input signal additional bit IOR B19 Inverted phase digital input signal for additional bit DAI T18 In phase input signal for sta...

Страница 25: ...D6 D7 D8 D9 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 In phase digital outputs for port D D0 is the LSB D9 is the MSB D0N D1N D2N D3N D4N D5N D6N D7N D8N D9N W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 Inverted pha...

Страница 26: ...Evaluation Kit User Guide 0904C BDC 09 07 STAGG A17 Staggered output mode selection signal BIST V17 Built In Self Test selection signal NC C19 Leave floating Table 5 1 ASTS8CSO01 Pinout Description C...

Страница 27: ...Package Information AT84CS001 EB Evaluation Kit User Guide 5 5 0904C BDC 09 07 5 2 Package Outline Figure 5 2 Package Outline Schematics...

Страница 28: ...Package Information 5 6 AT84CS001 EB Evaluation Kit User Guide 0904C BDC 09 07...

Страница 29: ...Number Package Temperature Range Screening Comments AT84XCS001TP EBGA 240 Ambient Prototype Please contact your local sales office AT84CS001VTP EBGA 240 Industrial V grade 40 C TC TJ 110 C Standard AT...

Страница 30: ...Ordering Information 6 2 AT84CS001 EB Evaluation Kit User Guide 0904C BDC 09 07...

Страница 31: ...AT84CS001 EB Evaluation Kit User Guide 7 1 0904C BDC 09 07 Section 7 Appendix 7 1 AT84CS001 EB Electrical Schematics Figure 7 1 Data I O Electrical Schematic...

Страница 32: ...Appendix 7 2 AT84CS001 EB Evaluation Kit User Guide 0904C BDC 09 07 Figure 7 2 Data I O Electrical Schematic 2 NC NC...

Страница 33: ...Appendix AT84CS001 EB Evaluation Kit User Guide 7 3 0904C BDC 09 07 Figure 7 3 Electrical Schematic of Power Supplies 1...

Страница 34: ...Appendix 7 4 AT84CS001 EB Evaluation Kit User Guide 0904C BDC 09 07 Figure 7 4 Electrical Schematic of Power Supplies 2...

Страница 35: ...Appendix AT84CS001 EB Evaluation Kit User Guide 7 5 0904C BDC 09 07 Figure 7 5 Electrical Schematic of Power Supplies 3...

Страница 36: ...Appendix 7 6 AT84CS001 EB Evaluation Kit User Guide 0904C BDC 09 07 7 2 AT84CS001 EB Board Layers Figure 7 6 Top Layer...

Страница 37: ...Appendix AT84CS001 EB Evaluation Kit User Guide 7 7 0904C BDC 09 07 Figure 7 7 Bottom Layer Figure 7 8 Equipped Board Top...

Страница 38: ...Appendix 7 8 AT84CS001 EB Evaluation Kit User Guide 0904C BDC 09 07 Figure 7 9 Equipped Board Bottom...

Страница 39: ...el 44 0 1245 493493 Fax 44 0 1245 492492 E Mail enquiries e2v com Southern Europe e2v sas 16 Burospace F 91572 Bi vres Cedex France Tel 33 0 16019 5500 Fax 33 0 16019 5529 E Mail enquiries fr e2v com...

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