E.F. Johnson Company 5100 ES, Руководство по обслуживанию

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January 2007 5100 ES Series Portable Radio Service Manual 5-15
Circuit Description
5.4.2 MPC870 Processor
The control processor, MPC870CZT66 is a derivative of the MPC885 PowerQUICC™
family which is a die-shrunk (0.18-micron) version of the MPC860 PowerQUICC family
and operates at speeds of up to 120 MHz on the MPC8xx core and up to 80 MHz (1:1
mode) on the external bus. The MPC870 has a 1.8-V core and 3.3-V I/O operation with 5-
V TTL compatibility. The MPC870 contains a PowerPC™ processor core. The MPC885
family is a PowerPC-architecture-based quad integrated communications controller
(PowerQUICC). The CPU on the MPC885 is the MPC8xx core, a 32-bit microprocessor
which implements the PowerPC architecture.
The MPC870(U1) is utilized as a control processor to that directs the operation of the
radio. Communication between the MPC870 and other functional blocks in the radio is
controlled though internal peripheral devices controllers. The device controllers provide
the following functions:
•
SPI Bus Controller – Communication link to volume control DAC,
HC08
Microcontroller, SPI FLASH, Logic Board SEM, and LCD display
• RS232 Controller – UDC RS232 link
• I2C Bus Controller – I2C bus control link to the Logic Board Codec
• Memory Controller – SRAM, FLASH, and HPI data interface and timing
• General Purpose I/O – I/O control signals to/from the RF Deck, LCD, HC08, Logic
Board, and UDC connector
5.4.3 Flash Memory
The UI Board Flash memory (U4) is a 16Mbit x 16, Intel 28F640P30 device. The Flash
memory operates off a 1.8 Vdc core and 3.3 Vdc I/O voltages.
5.4.4 SRAM
The SRAM (U6) is a Cypress CY62167DV30 16 Mbit device in a 2Mx16 memory
configuration. The device is powered from a linear regulator that is connected directly to
the radio battery. This allows for battery backup operation in which data stored in the
SRAM is retained when the radio is turned off. A logic gate (U22) disables the SRAM
chip select when normal UI Board power is turned off and places the SRAM in a low
power consumption state.