Dynamic Engineering PCIe8LSwVPX3U, Руководство пользователя

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Embedded Solutions Page 12
VPX Module Backplane IO Interface Pin Assignment
The figure below gives the pin assignments for the VPX Module IO Interface – from
P2/J2 to the PCIe8LSwVPX3U connector. Also see the User Manual for your VPX
board for more information.
SCSI P2 – VPX J2  USER VPX P2
SCSI II [P2] VPX[J2] User VPX [P2]
1 35 G16 H16 E16 F16
2 36 C16 D16 B16 C16
3 37 E15 F15 D15 E15
4 38 A15 B15 A15 B15
5 39 G14 H14 E14 F14
6 40 C14 D14 B14 C14
7 41 E13 F13 D13 E13
8 42 A13 B13 A13 B13
9 43 G12 H12 E12 F12
10 44 C12 D12 B12 C12
11 45 E11 F11 D11 E11
12 46 A11 B11 A11 B11
13 47 G10 H10 E10 F10
14 48 C10 D10 B10 C10
15 49 E9 F9 D9 E9
16 50 A9 B9 A9 B9
17 51 G8 H8 E8 F8
18 52 C8 D8 B8 C8
19 53 E7 F7 D7 E7
20 54 A7 B7 A7 B7
21 55 G6 H6 E6 F6
22 56 C6 D6 B6 C6
23 57 E5 F5 D5 E5
24 58 A5 B5 A5 B5
25 59 G4 H4 E4 F4
26 60 C4 D4 B4 C4
27 61 E3 F3 D3 E3
28 62 A3 B3 A3 B3
29 63 G2 H2 E2 F2
30 64 C2 D2 B2 C2
31 65 E1 F1 D1 E1
32 66 A1 B1 A1 B1
33 67 Open, +3 or GND via J1 silk screen defined
34 68 Open, +3 or GND via J2
FIGURE 2 PCIE8LSWVPX3U P2/J2/USER P2 IO
Read table:
P2-1 = J2-G16, P2-35 = J2-H16
GND1-72 are connected to GND. C1, D1 etc. SE7-0 are open I1, I3, I5 etc.