Chapter 4
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SDRAM RAS-to-CAS Delay: When SDRAM is refreshed, both rows and columns are addressed
separately. This setting item select the delay cycles between the assertion of RAS# and CAS#.
SDRAM RAS Precharge Time: This defines the length of time for Row Address Strobe to
precharge.
SDRAM CAS Latency Time: This defines the length of time for Column Address Strobe to
precharge. The settings are 2 or 3.
DRAM Data Integrity Mode: Choose ECC or Non-ECC according to the type of DIMM
installed.
System/Video BIOS Cacheable: Choose Enabled or Disabled. “Enabled” allows system/video
BIOS be cacheable.
Video RAM Cacheable: Select Enabled or Disabled. “Enabled” allows video RAM to be
cacheable.
Memory Hole At 15M-16M: Choose Enabled or Disabled. “Enabled” allows some linear VGA
cards to run larger frame port, or it can be reserved for some operation system.
Passive Release: Choose Enabled or Disabled. When Enabled, CPU to PCI bus access is
allowed during passive released. Otherwise, the arbiter only accepts another PCI master access to
local DRAM.
Delay Transaction: Choose Enabled or Disabled. The chipset has an embedded 32-bit posted
write buffer to support delay transactions cycles. Choose Enabled to support compliance with
PCI specification 2.1.
AGP Aperture Size (MB): Choose the size of the Accelerated Graphic Port (AGP) aperture.
The aperture is a portion of the PCI memory address range dedicated for graphics memory
address space. Host cycles that hit the aperture range are forwarded to the AGP without any
translation. The available options are 4, 8, 16, 32, 64, 128 and 256MB.
H/W Reset Protection: Enabled to disable the function of H/W reset button.
