AP63300/1-EVM
3.8V TO 32V INPUT, 3A LOW IQ SYNCHRONOUS BUCK WITH
ENCHANCED EMI REDUCTION
AP63300/AP63301
Document number: DS42002 Rev. 3 - 2
5 of 11
September 2019
© Diodes Incorporated
MEASUREMENT/PERFORMANCE GUIDELINES:
1) When measuring the output voltage ripple, maintain the shortest possible ground lengths on the
oscilloscope probe. Long ground leads can erroneously inject high frequency noise into the
measured ripple.
2) For efficiency measurements, connect an ammeter in series with the input supply to measure the
input current. Connect an electronic load to the output for output current.
Setting the Output Voltage of AP63300
1) Setting the output voltage
The AP63300 features external programmable output voltage by using a resistor divider network
R3 and R1 as shown in the typical application circuit. The output voltage is calculated as below,
1
3
1
8
.
0
R
R
R
V
OUT
First, select a value for R1 according to the value recommended in the table 1. Then, R3 is
determined. The output voltage is given by Table 1 for reference. For accurate output voltage, 1%
tolerance is required.
2) Output feed-forward capacitor selection
The AP63300 has the internal integrated loop compensation as shown in the function block
diagram. The compensation network includes a 18k resistor and a 7.6nF capacitor. Usually, the
type II compensation network has a phase margin between 60 and 90 degree. However, if the
output capacitor has ultra-low ESR, the converter results in low phase margin. To increase the
converter phase margin, a feed-forward cap C4 is used to boost the phase margin at the converter
cross-over frequency
C
f
. The feed-forward capacitor is given by Table 1 for reference. The feed-
forward capacitor is calculated as below,
3
2
1
R
C
f
C
ff
Table 1. Resistor selection for output voltage setting
Vo
R3
R1
C4
C6-C8
1.8V
77.5 K
Ω
62 K
Ω
100pF
22uFx2
2.5V
131 K
Ω
62 K
Ω
100pF
22uFx2
3.3V
182 K
Ω
62 K
Ω
100 pF
22uFx2
5V
157 K
Ω
30 K
Ω
100 pF
22uFx2
12V
249 K
Ω
18 K
Ω
56 pF
22uFx4
