AMBE-2000™ Vocoder Chip Users Manual
Version 4.92, June, 08
DVSI Confidential Proprietary, Subject to Change
Page 16
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3.3
Clock and Reset Timing
To reset the AMBE-2020™ chip, the reset signal must be held low for a minimum of 50 µs. The recovery time from reset is
approximately 95 msec. In other words, 95 msec after the rising edge of the reset signal the AMBE-2020™ starts processing
PCM samples. The first packet will be ready after 252 PCM samples are read.
Figure 3-A X2/CLKIN and CLKOUT Timing Diagram
Table 3-A X2/CLKIN and CLKOUT Timing Parameters
Reference
Parameter
Min
Max
Units
t
c
(CI)
Cycle time, X2/CLKIN
Integer PLL multiplier N (N=4)
20
400
ns
t
f
(CL)
Fall time, X2/CLKIN
4
ns
t
r
(CL)
Rise time, X2/CLKIN
4
ns
t
w
(CIL)
Pulse duration, X2/CLKIN low
6
ns
t
w
(CIH)
Pulse duration, X2/CLKIN high
6
ns
t
P
Transitory phase, PLL lock-up time
50
µ
s
t
c
(CO)
Cycle time, CLKOUT (typical is t
c
(CI)/4)
15
ns
t
d
(CIH-CO)
Delay time, X2/CLKIN high/low to CLKOUT high/low
4
16
ns
t
f
(CO)/t
r
(CO)
Fall/Rise time, CLKOUT (typical is 2 ns)
t
w
(COL)
Pulse duration, CLKOUT low
H-4
H
ns
t
w
(COH)
Pulse duration, CLKOUT high
H-4
H
ns
•
CLKOUT is shown for reference only it is not connected.
•
H=7.629 ns
~ ~
~ ~
~ ~
Unstable
~ ~
~ ~
tp
t
c
(CI)
t
c
(CO)
t
d
(CIH-CO)
t
w
(CIH)
t
w
(CIL)
t
w
(COH)
t
w
(COL)
t
r
(CI)
t
f
(CI)
t
r
(CO)
t
f
(CO)
X2/CLKIN
CLKOUT
