Spectrum Digital, Inc
2-6
TMS320C6413/C6418 EVM Module Technical Reference
2.1.7 LCD Interface
The Liquid Crystal Display (LCD) is a write only interface. It is interfaced via an 8-bit
shift register.
Two locations are used when interfacing the LCD panel. Allowing the address bit of the
interface to be directly programmed. The shift clock frequency is 5 megahertz.
Writing register LCD0 sets the LCD address line A0 to 0. Writing register LCD1 sets the
LCD address line A0 to 1. The write operation to either of these locations starts an
internal shift register serializing the data into an 8-bit sequence to the displays.
The table below shows the relationship of the DSP data bits to the LCD data bits.
The figure below shows the LCD data transfer timing. the CPLD automatically
generates this timing.
After any write operations the CPLD sets the LCD BUSY bit in the C6413/C6418 EVM
interface Register as the output is being serialized. The user should check this bit prior
to starting another write operation. When LCD BUSY is high, the LCD shift register is
busy, when is low the shift register is ready.
Table 6: LCD Interface
D7
D6
D5
D4
D3
D2
D1
D0
LCD D7
LCD D6
LCD D5
LCD D4
LCD D3
LCD D2
LCD D1
LCD D0
LCDCLK
LCD Address
LCD Data
D7
D6
D5
D4
D3
D2
D1
D0
Figure 2-3, LCD Data Transfer Timing
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