DIGITAL-LOGIC SM800/900DK, Техническое руководство пользователя

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DIGITAL-LOGIC AG
SM800/900DK Technical Manual V1.2B
75
13.4. Clocks
13.4.1. Clock Layout Guidelines
Series matching resistors are required. Not used PCI_CLK[1:0] signals should be loaded by 47pF to reduce
the EMI noise.
Resistor Value: 10 Ohms in series are recommended for better EMI results.
Placement: As near as possible to the driver pin (less than 1“).
The clock signals must have the same length (ideally 50mm) on the external PCB.
Name Pin Internal Length Information to the signal integrity
PCI_CLK0 A68 50mm On the external PCBV, this clock signal should be 50mm long
PCI_CLK1 B68 50mm On the external PCBV, this clock signal should be 50mm long
CLK_LAN 100mm On the module only
CLK_PCI2ISA 100mm On the module only
If there are more PCI devices than PCI clock lines, clock replicators are needed. Refer to the sample
schematics (5
th
of the 16 pages) to see an example. We recommend the ICS91305 to expand 1 clock to 4
clocks. Never share one clock line to multiple PCI devices.
13.5. ITP / JTAG Signals
Name Type Voltage Description
JTAG_TDO O V_CPUPU
JTAG Test Data Out: Serial output port TAP instructions and
data are shifted out of the processor from this port.
JTAG_TDI I V_CPUPU
JTAG Test Data In: Serial input port. TAP instructions and
data are shifted into the processor from this port.
JTAG_TMS I V_CPUPU
JTAG Test Mode Select: Controls the TAP controller change
sequence.
JTAG_TCLK I V_CPUPU
JTAG Test Clock: Testability clock for clocking (the JTAG
boundary scan sequence.
If not used, the pin remains unconnected.