DIGITAL-LOGIC SM800/900DK, Техническое руководство пользователя

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DIGITAL-LOGIC AG
SM800/900DK Technical Manual V1.2B
73
13.3.3. PCI Signal Descriptions
Name Type Voltage Description
AD[31:0] I/O PCI +3.3 Address/Data. The standard PCI address and data lines. The address is
driven with FRAME# assertion, and data is driven or received in ensuing
clocks.
C/BE[3:0]# I/O PCI +3.3 PCI Bus Command and Byte Enables. During the address phase of a PCI
transaction, when FRAME# is active, C/BE[3:0]# defines the bus command.
During the data phase of a transaction, C/BE[3:0]# enables the data byte.
C/BE[3:0]# are outputs when the GEODE CS5536 companion device is a PCI
master, and inputs when it is a PCI slave.
FRAME# I/O PCI +3.3
PCI Cycle Frame. FRAME# is asserted to indicate the start and duration of a
transaction. It is de-asserted on the final data phase.
FRAME# is an input when the GEODE CS5536 companion device is a PCI
slave.
Internal 10k Ω pull-up to +3.3V. This signal is in TRI-STATE mode after reset.
DEVSEL# I/O PCI +3.3 PCI Device Select. DEVSEL# is asserted by a PCI slave to indicate to a PCI
master and subtractive decoder that it is the target of the current transaction.
As an input, DEVSEL# indicates a PCI slave has responded to the current
address.
As an output, DEVSEL# is asserted one cycle after the assertion of FRAME#
and remains asserted to the end of a transaction as the result of a positive
decode. DEVSEL# is asserted four cycles after the assertion of FRAME# if
DEVSEL# has not been asserted by another PCI device, when the Geode
CS5536 companion device is programmed to be the subtractive decode agent.
Internal 10k Ω pull-up to +3.3V. This signal is in TRI-STATE mode after reset.
IRDY# I/O PCI +3.3 PCI Initiator Ready. IRDY# is driven by the master to indicate valid data on a
write transaction, or that it is ready to receive data on a read transaction.
When the GEODE CS5536 companion device is a PCI slave, IRDY# is an input
that can delay the beginning of a write transaction or the completion of a read
transaction.
Wait cycles are inserted until both IRDY# and TRDY# are asserted together.
Internal 10k Ω pull-up to +3.3V. This signal is in TRI-STATE mode after reset.
TRDY# I/O PCI +3.3 PCI Target Ready. TRDY# is asserted by a PCI slave to indicate it is ready to
complete the current data transfer.
TRDY# is an input that indicates a PCI slave has driven valid data on a read or a
PCI slave is ready to accept data from the GEODE CS5536 companion device
on a write.
TRDY# is an output that indicates the GEODE CS5536 companion device has
placed valid data on AD[31:0] during a read or is ready to accept the data from a
PCI master on a write.
Wait cycles are inserted until both IRDY# and TRDY# are asserted together.
Internal 10k
Ω
pull-up to +3.3V. This signal is in TRI-STATE mode after reset.
Continued…