DIGITAL-LOGIC AG
MSM800SEV/SEL/BEV/XEV/XEL Detailed Manual V1.7
59
CMOS Map
continued...
Location
Description
2Dh
Reserved
2Eh
High Byte of Checksum - Locations 10h to 2Dh
2Fh
Low Byte of Checksum - Locations 10h to 2Dh
30h
Extended RAM (kB) detected by POST - Low Byte
31h
Extended RAM (kB) detected by POST - High Byte
32h
BCD Value for Century
33h
Base Memory Installed
Bit 7
= Flag for Memory Size
0
=
640kB
1
=
512kB
Bits 6-0 = Reserved
34h
Minor CPU Revision
Differentiates CPUs within a CPU type (i.e., 486SX vs 486
DX, vs 486 DX/2). This is crucial for correctly determining
CPU input clock frequency. During a power-on reset, Reg DL
holds minor CPU revision.
35h
Major CPU Revision
Differentiates between different CPUs (i.e., 386, 486,
Pentium). This is crucial for correctly determining CPU input
clock frequency. During a power-on reset, Reg DH holds
major CPU revision.
36h
Hotkey Usage
Bits 7-6 = Reserved
Bit 5
= Semaphore for Completed POST
Bit 4
= Semaphore for 0 Volt POST
(not currently used)
Bit 3
= Semaphore for already in SCU menu
Bit 2
= Semaphore for already in PM menu
Bit 1
= Semaphore for SCU menu call pending
Bit 0
= Semaphore for PM menu call pending
40h-7Fh
Definitions for these locations vary depending on the chipset.
Содержание MSM800BEV
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