DIGITAL-LOGIC MSM800BEV, Техническое руководство пользователя

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DIGITAL-LOGIC AG
MSM800SEV/SEL/BEV/XEV/XEL Detailed Manual V1.7
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/SMEMR, input/output
These signals instruct the memory devices to drive data onto the data bus for the first MByte. /SMEMR
is active on all memory read cycles. /SMEMR may be driven by any microprocessor or DMA controller
in the system. When a microprocessor on the I/0 channel wishes to drive /SMEMR, it must have the
address lines valid on the bus for one system clock period before driving /SMEMR active. The signal is
active low .
/SMEMW, input/output
These signals instruct the memory devices to store the data present on the data bus for the first
MByte. /SMEMW is active in all memory read cycles. /SMEMW may be driven by any microprocessor
or DMA controller in the system. When a microprocessor on the I/O channel wishes to drive /SMEMW,
it must have the address lines valid on the bus for one system clock period before driving /SMEMW
active. Both signals are
active low
.
SYSCLK, output
This is an 8MHz system clock. It is a synchronous microprocessor cycle clock with a cycle time of 167
nanoseconds. The clock has a 66% duty cycle. This signal should only be used for synchronization.
TC, output
Terminal Count: provides a pulse when the terminal count for any DMA channel is reached. The TC
completes a DMA-Transfer. This signal is expected by the onboard floppy disk controller. Do not use
this signal, because it is internally connected to the floppy controller.
/0WS, input
The Zero Wait State (/0WS) signal tells the microprocessor that it can complete the present bus cycle
without inserting any additional wait cycles. In order to run a memory cycle to a 16bit device without
wait cycles, /0WS is derived from an address decode gated with a Read or Write command. In order to
run a memory cycle to an 8bit device with a minimum of one-wait states, /OWS should be driven active
one system clock after the Read or Write command is active, gated with the address decode for the
device. Memory Read and Write commands to an 8bit device are active on the falling edge of the
system clock. /0WS is
active low
and should be driven with an open collector or tri-state driver
capable of sinking 20mA.
12V, +/- 5%
This signal is used only for the flat panel supply.
GROUND = 0V
This is used for the entire system.
VCC, +5V +/- 0.25V
This signal is used for logic and hard/floppy disk supply.
For further information about PC/104 and PC/104plus, please refer to the PC/104 Specification
Manual which is available on the internet:
http://www.digitallogic.com (manuals).
3.2. PC104+ Bus
AD[31:00]
Address and Data are multiplexed. A bus transaction consists of an address cycle followed by one or
more data cycles.
C/BE[3:0]*
Bus Command/Byte Enables are multiplexed. During the address cycle, the command is defined.
During the Data cycle, they define the byte enables.
PAR
Parity is even on AD[31:00] and C/BE[3:0]* and is required.