Zybo Z7 Board Reference Manual
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
Page
30
of
31
Pmod JA
Pmod JB*
Pmod JC
Pmod JD
Pmod JE
Pmod JF
Pmod Type
XADC
High-Speed
High-Speed
High-Speed
Standard
MIO
Pin 9
J16
V6
T12
V17
T17
MIO-14
Pin 10
J14
W6
U12
V18
Y17
MIO-15
*Pmod JB is not available on the Zybo Z7-10
Table 16.1. Zybo Z7 Pmod Pinout
16.1 Standard Pmod
The standard Pmod ports are connected to the Zynq PL via 200 Ohm series resistors. The series resistors prevent
short circuits that can occur if the user accidentally drives a signal that is supposed to be used as an input. The
downside to this added protection is that these resistors can limit the maximum switching speed of the data
signals. If the Pmod being used does not require high-speed access, then the standard Pmod port should be used
to help prevent damage to the devices.
16.2 MIO Pmod
The MIO Pmod port is connected to the MIO bus in the Zynq PS via 200 Ohm series resistors. Like the standard
Pmod port, these series resistors add protection at the cost of maximum switching speed. Since these data signals
are connected to the MIO interface, they can only be accessed by the PS peripheral controller cores. The GPIO,
UART, I2C, and SPI cores can all be used to drive devices connected to this Pmod. Note that the pin layout of the
UART and I2C cores will not align perfectly with the typical Pmod pinouts for these interfaces. This means that
UART or I2C devices connected to this Pmod may require some of the pins to be swapped around externally using
individual wires between the Zybo Z7 and the Pmod.
16.3 Dual Analog/Digital Pmod (XADC Pmod)
The
Pmod port labeled “XADC” is wired to the auxiliary analog input pins of the PL. Depending on the Zynq PL
configuration, this port can be used to input differential analog signals to the analog-to-digital converter inside the
Zynq XADC core. Any or all pairs in the port can be configured either as analog input or digital input-output.
In analog input mode, the voltage on these pins must be limited to 1V peak-to-peak. In digital mode, the regular
VCCO-dependent limits apply. See Xilinx datasheets for more information.
The Dual Analog/Digital Pmod on the Zybo Z7 differs from the rest in the routing of its traces. The eight data
signals are grouped into four pairs, with the pairs routed closely coupled for better analog noise immunity. Pins 1
and 7, pins 2 and 8, pins 3 and 9, and pins 4 and 10 are paired up. Furthermore, each pair has a partially loaded
anti-alias filter laid out on the PCB. The filter does not have capacitors C101-C104 loaded. In designs where such
filters are desired, the capacitors can be manually loaded by the user.
NOTE: The coupled routing and the anti-alias filters might limit the data speeds when used for digital signals.
The XADC core within the Zynq is a dual channel 12-bit analog-to-digital converter capable of operating at 1 MSPS.
Either channel can be driven by any of the auxiliary analog input pairs connected to the XADC port. The XADC core
is controlled and accessed from the PL via the Dynamic Reconfiguration Port (DRP). The DRP also provides access
to voltage monitors that are present on each of the Zynq's power rails, and a temperature sensor that is internal to
the Zynq. For more information on using the XADC core, refer to the Xilinx document titled “7 Series FPGAs and
Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-
Digital Converter.” It is also possible to
access the XADC core directly using the PS, via the “PS
-
XADC” interface. This interface is described in full in chapter
30 of the Zynq Technical Reference Manual.
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