Zybo Z7 Board Reference Manual
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
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16 MiB (16,777,216 bytes)
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1-bit, 2-bit, and 4-bit bus widths supported
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General use clock speeds up to 100 MHz, translating to 400 Mbps in Quad-SPI mode
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Zynq configuration clock speeds up to 94 MHz.
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Powered from 3.3V
The Flash memory is used to provide non-volatile code and data storage. It can be used to initialize the PS and PL
of the Zynq device with a Zynq Boot Image (also known as BOOT.BIN) generated using Xilinx tools such as Petalinux
or Xilinx SDK. For information on booting the Zybo Z7 with a Zynq Boot image, see section “2.2 Quad SPI Boot
Mode”.
The Flash is also commonly used to store non-configuration data needed by the application. If doing this from a
bare-metal application, The flash memory can be freely accessed using standalone libraries included with a Xilinx
SDK BSP project. If doing this from a Petalinux generated embedded Linux system, the Flash can be partitioned as
desired and mounted/accessed like a standard MTD block device. See the Petalinux and Xilinx SDK documentation
for more information.
The Flash connects to the Quad-SPI Flash controller of the Zynq-7000 PS via pins in MIO Bank 0/500 (specifically
MIO[1:6,8]), as outlined in the Zynq Technical Reference Manual. Quad-SPI feedback mode is used, thus
qspi_sclk_fb_out/MIO[8] is left to freely toggle and is connected only to a 20K pull-up resistor to 3.3V. This allows a
Quad-SPI clock frequency greater than FQSPICLK2. The details of these connections do not need to be known when
using the Zybo Z7 Vivado Board files, as they will automatically configure your project to work correctly with the
on-board Flash.
A globally unique MAC address is programmed into the One-Time-Programmable (OTP) region of the Flash on each
Zybo Z7 at the factory. For more information on this, see section “10 Ethernet”.
The OTP region also includes a factory-programmed read-only 128-bit random number. The very lowest address
range [0x00;0x0F] can be read to access the random number. See the Spansion S25FL128S datasheet for
information on this random number and accessing the OTP region.
5
Oscillators/Clocks
The Zybo Z7 provides a 33.3333 MHz clock to the Zynq PS_CLK input, which is used to generate the clocks for each
of the PS subsystems. The 33.3333 MHz input allows the processor to operate at a maximum frequency of
667 MHz and the DDR3 memory controller to operate at a maximum clock rate of 533 MHz (1066 MT/s). The Zybo
Z7 board files, available on the
Zybo Z7 Resource Center
, will automatically configure the Zynq processing system
IP core in Vivado to work with all PS attached devices, including the 33.3333 MHz input oscillator.
The PS has a dedicated PLL capable of generating up to four reference clocks, each with settable frequencies, that
can be used to clock custom logic implemented in the PL. Additionally, The Zybo Z7 provides an external
125 MHz reference clock directly to pin K17 of the PL. The external reference clock allows the PL to be used
completely independently of the PS, which can be useful for simple applications that do not require the processor.
The PL of the Zynq-Z7010 a
lso includes two MMCM’s and two PLL’s that can be used to generate clocks with
precise frequencies and phase relationships. Any of the four PS reference clocks or the 125 MHz external reference
clock can be used as an input to the MMCMs and PLLs. For a full description of the capabilities of the Zynq PL
clocking resources, refer to the “7 Series FPGAs Clocking Resources User Guide” available from Xilinx.
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