background image

JTAG-HS2 Reference Manual 

 

 

Doc: 502-249 

 

page 5 of 5 

Figure 7 

TMS/TDI

TCK

TDO

T

CKL

T

CKH

T

CK

T

CD

T

SU

T

HD

 

 
 

Figure 8 

Symbol 

Parameter 

Min 

Max 

T

CK

 

T

CK

 period 

33.3ns  125µs 

T

CKH

, T

CKL

 

T

CLK

 pulse width 

16.6ns  62.5µs 

T

CD

 

T

CLK

 to TMS, TDI  0 

15ns 

T

SU

 

TDO Setup time 

19ns 

 

T

HD

 

TDO Hold time 

 

 

DC Operating Characteristics

 

 

Symbol 

Parameter 

Min 

Typ 

Max 

Unit 

VDD (VREF) 

I/O reference/supply voltage 

1.65 

2.5/3.3 

5.5 

Volts 

TDO 

Input High Voltage (V

IH

1.62 

 

5.5 

Volts 

Input Low Voltage (V

IL

 

0.65 

Volts 

TMS, TCK, TDI  

Output High (V

OH

0.85 x Vdd 

0.95 x Vdd 

Vdd 

Volts 

Output Low (V

OL

0.05 x Vdd 

0.15 x Vdd 

Volts 

 

 
AC Operating Characteristics

 

 
The JTAG-HS2 JTAG signals and SPI 
operate according to the timing diagram in 
Figure 7. The HS2 supports TCK frequencies 
from 30 MHz to 8 KHz at integer divisions of 
30MHz from 1 to 3750. Common frequencies 
include 30MHz, 15MHz, 10MHz, 7.5MHz, and 
6HMz. (See Figure 8) 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

 

Copyright Digilent, Inc. All rights reserved.  Other product and company names mentioned may be trademarks of their respective owners. 

Содержание JTAG-HS2

Страница 1: ... up to 30MBit sec See figure 1 To function correctly the HS2 s Vdd pin must be tied to the same voltage supply that drives the JTAG port on the FPGA The JTAG bus can be shared with other devices as systems hold JTAG signals at high impedance except when actively driven during programming The HS2 comes included with a standard Type A to Micro USB cable that attaches to the end of the module opposit...

Страница 2: ... Digilent s website This Adept software includes a full featured programming environment and a set of public application programming interfaces API that allow user applications to directly drive the JTAG chain With the Adept SDK users can create custom applications that will drive JTAG ports on virtually any device Users may utilize the API s provided by the SDK to create applications that can dri...

Страница 3: ...OC Target System 0 Target System 1 Target System N TMSC TDIC TCKC TDOC TMSC TDIC TCKC TDOC TMS TDI TCK TDO Host JTAG HS2 DTS The Adept SDK provides an example application that demonstrates how to communicate with a Class T4 TAP controller using the MScan OScan0 and OScan1 scan formats Design Notes The JTAG HS2 uses high speed three state buffers to drive the TMS TDI and TCK signals These buffers a...

Страница 4: ... format bit period and the level of the TCK pin determine which device is allowed to drive the TMS pin A drive conflict may occur when the HS2 and TS disagree on the current scan format setting or bit period In the event that a drive conflict occurs the 100 ohm resistor between the TMS buffer and output pin will limit the maximum current to 50 mA to prevent any damage from occurring to the JTAG HS...

Страница 5: ... TDO Input High Voltage VIH 1 62 5 5 Volts Input Low Voltage VIL 0 0 65 Volts TMS TCK TDI Output High VOH 0 85 x Vdd 0 95 x Vdd Vdd Volts Output Low VOL 0 0 05 x Vdd 0 15 x Vdd Volts AC Operating Characteristics The JTAG HS2 JTAG signals and SPI operate according to the timing diagram in Figure 7 The HS2 supports TCK frequencies from 30 MHz to 8 KHz at integer divisions of 30MHz from 1 to 3750 Com...

Отзывы: