The on-board PHY implements Layer 1 in the Ethernet stack, interfacing between the physical copper medium and the media
access control (MAC). The MAC must be implemented in the FPGA and mapped to the PHY’s RGMII interface. Vivado-
based design can use the Xilinx AXI Ethernet Subsystem IP core to implement the MAC and wire it to the processor and the
memory subsystem. At the time of writing the IP core needed to be licensed separately.
On an Ethernet network each node needs a unique MAC address. To this end the Genesys 2 comes with a MAC address pre-
programmed in a special one-time programmable region (OTP Region 1) of the Quad-SPI Flash6. This unique identifier can be
read with the OTP Read command (0x4B). The out-of-box Ethernet demo uses the unique MAC to allow connecting several
Genesys 2 boards to the same network.
A downloadable demonstration project can be found on the
Genesys 2 wiki page
(https://reference.digilentinc.com/genesys2:genesys2)
.
The Genesys 2 board includes several oscillators and crystals, of which two are connected to the FPGA. One differential LVDS
200MHz oscillator is connected to MRCC GPIO () pins AD12/AD11 in bank 33. This input clock can drive MMCMs or PLLs
to generate clocks of various frequencies and with known phase relationships that may be needed throughout a design. Some
rules restrict which MMCMs and PLLs may be driven by the 200MHz input clock. For a full description of these rules and of
the capabilities of the Kintex-7 clocking resources, refer to the “7 Series FPGAs Clocking Resources User Guide” (
ug472
(http://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf)
) available from Xilinx.
Xilinx offers the Clocking Wizard IP core to help users generate the different clocks required for a specific design. This wizard
will properly instantiate the needed MMCMs and PLLs based on the desired frequencies and phase relationships specified by
the user. The wizard will then output an easy to use wrapper component around these clocking resources that can be inserted
into the user’s design. The clocking wizard can be accessed from within the Vivado Block Design or Core Generator tools.
The second oscillator outputs a differential LVDS 135MHz clock which enters the FPGA on MGTREFCLK pins. This
connects to clock primitives dedicated to the gigabit transceivers and is used for DisplayPort designs.
8. Oscillators/Clocks
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